Signal routing between memory and memory controller

An integrated circuit (IC) layout, comprising:

• a plurality of memory blocks arranged in a set of rows and a set of columns;
• a memory controller arranged in parallel to the set of rows and not the set of columns or the set of columns and not the set of rows;
• and
• a first plurality of metal routes that are created over the plurality of memory blocks and enable signal routing between the plurality of memory blocks and the memory controller, wherein the first plurality of metal routes are created such that each memory block of the plurality of memory blocks is coupled with the memory controller by way of a first set of metal routes of the first plurality of metal routes, wherein any other metal route arranged over the plurality of memory blocks which enable signaling between the plurality of memory blocks and the memory controller is parallel to the first plurality of metal routes, and wherein the first plurality of metal routes are parallel to the set of columns when the memory controller is arranged in parallel to the set of rows and the first plurality of metal routes are parallel to the set of rows when the memory controller is arranged in parallel to the set of columns, wherein the first plurality of metal routes are created by way of a set of metal layers associated with an IC, wherein each metal layer of the set of metal layers corresponds to one of a horizontal metal layer and a vertical metal layer, and wherein a number of metal layers included in the set of metal layers is determined based on a number of available metal layers in the IC and a number of metal layers utilized within the plurality of memory blocks.

A method for enabling signal routing on an integrated circuit (IC) layout using an electronic design automation tool, the method comprising:

• arranging a plurality of memory blocks of a memory in a set of rows and a set of columns;
• arranging a memory controller in parallel to the set of rows and not the set of columns or the set of columns and not the set of rows;
• and
• creating a first plurality of metal routes over the plurality of memory blocks such that each memory block of the plurality of memory blocks is coupled with the memory controller by way of a first set of metal routes of the first plurality of metal routes, wherein any other metal route arranged over the plurality of memory blocks which enable signaling between the plurality of memory blocks and the memory controller is parallel to the first plurality of metal routes, and wherein the first plurality of metal routes are parallel to the set of columns when the memory controller is arranged in parallel to the set of rows and the first plurality of metal routes are parallel to the set of rows when the memory controller is arranged in parallel to the set of columns, wherein the first plurality of metal routes enable the signal routing between the plurality of memory blocks and the memory controller.