Logical node layout method and apparatus, computer device, and storage medium

A logical node layout apparatus applicable to a many-core system, wherein among a plurality of processing nodes of the many-core system, the processing nodes located at an edge of a network-on-chip are edge processing nodes, and the remaining processing nodes are internal processing nodes, and the apparatus comprises:

• a routing information acquisition module configured to acquire multiple pieces of routing information, each of which comprises two logical nodes and a data transmission amount between the two logical nodes;
• a current routing determination module configured to determine a piece of unprocessed routing information with a maximum data transmission amount as current routing information;
• a mapping module configured to map each unlocked logical node of the current routing information to one unlocked processing node, and lock the mapped logical node and processing node, wherein if there is an unlocked edge processing node, the unlocked logical node is mapped to the unlocked edge processing node,
• if there is at least one unlocked logical node, the current routing determination module is enabled to work.