Integrated circuit and method of manufacturing same

A method of manufacturing an integrated circuit comprising:

• positioning a first set of conductive features by a first mask, the first set of conductive features being in a first direction and a first level of the integrated circuit;
• manufacturing a second set of conductive features in a second direction different from the first direction, the second set of conductive features being in a second level of the integrated circuit, the second level being different from the first level, the second set of conductive features comprises:
• a first conductive feature of the second set of conductive features corresponding to a gate terminal of a first p-type transistor;
• and
• a second conductive feature of the second set of conductive features corresponding to a gate terminal of a first n-type transistor;
• and
• positioning a third set of conductive features on a third level below at least the first level, and extending in the second direction, the third set of conductive features including a first conductive feature of the third set of conductive features that overlaps a first active region and a second active region, and that corresponds to at least a first contact of a first dummy transistor;
• wherein the first conductive feature of the second set of conductive features and the second conductive feature of the second set of conductive features are separated from each other in at least the second direction;
• the first n-type transistor is part of a first transmission gate;
• and
• the first p-type transistor is part of a second transmission gate.

An integrated circuit, comprising:

• a first set of conductive traces in a first level of the integrated circuit, the first set of conductive traces extending in a first direction;
• a second set of conductive traces in a second level of the integrated circuit different from the first level, the second set of conductive traces extending in a second direction different from the first direction, the second set of conductive traces including:
• a first conductive trace of the second set of conductive traces corresponding to a gate terminal of a first p-type transistor;
• a second conductive trace of the second set of conductive traces corresponding to a gate terminal of a first n-type transistor;
• and
• a third conductive trace of the second set of conductive traces corresponding to a gate terminal of a first dummy transistor and a gate terminal of a second dummy transistor;
• and
• wherein the first conductive trace of the second set of conductive traces and the second conductive trace of the second set of conductive traces are separated from each other in at least the second direction;
• the first conductive trace of the second set of conductive traces is electrically coupled to the second conductive trace of the second set of conductive traces by at least the third conductive trace of the second set of conductive traces;
• and
• the first n-type transistor being part of a first transmission gate;
• and
• the first p-type transistor being part of a second transmission gate.