US 11,694,012 B2Granted

Multiplexer

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei

Life of this patent

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Abstract

A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Claims20

Dependent claims

A multiplexer configured to receive first, second, third and fourth data signals and first, second, third and fourth select signals, and to output a selected one of the first, second, third and fourth data signals in response to the first, second, third and fourth select signals, the multiplexer comprising:

first and second fins each extending in an X-axis direction;
a first AO122 circuit including a first plurality of poly gates extending in a Y-axis direction perpendicular to the X-axis direction;
a second AO122 circuit including a second plurality of poly gates extending in the Y-axis direction;
an ND2 circuit including a third plurality of poly gates extending in the Y-axis direction, the third plurality of poly gates configured to receive first and second outputs from the first and second AO122 circuits, respectively;
wherein the second plurality of poly gates includes a first segmented gate having first and second segments separated from one another such that the first segment contacts the first fin and the second segment contacts the second fin, and wherein the first segment of the first segmented gate is configured to receive one of the first, second, third or fourth data signals, and the second segment of the first segmented gate is configured to receive one of the first, second, third or fourth select signals.

2 more elements

first and second fins each extending in an X-axis direction;
a first AO122 circuit including a first plurality of gates extending in a Y-axis direction perpendicular to the X-axis direction and contacting the first and second fins;
a second AO122 circuit including a second plurality of gates extending in the Y-axis direction and contacting the first and second fins;
an ND2 circuit including a third plurality of gates extending in the Y-axis direction, the third plurality of gates configured to receive first and second outputs from the first and second AO122 circuits, respectively;
and
an inactive structure extending in the Y-axis direction and contacting the first and second fins, the inactive structure situated between the first plurality of gates and the third plurality of gates.

3 more elements

A method, comprising:

providing an input logic circuit that includes first and second fins each extending in an X-axis direction and first, second, third, fourth, fifth, sixth, seventh and eighth gates extending in a Y-axis direction perpendicular to the X-axis direction and contacting the first and second fins;
providing an output logic circuit that includes a ninth gate extending in the Y-axis direction and contacting the first and second fins;
receiving first, second, third and fourth data signals, respectively, by the first, second, third and fourth gates;
receiving first, second, third and fourth select signals, respectively, by the fifth, sixth, seventh and eighth gates;
providing an output signal by the input logic circuit based on the first, second, third and fourth data signals and the first, second, third and fourth select signals at an intermediate node;
receiving the output signal at the intermediate node by the output logic circuit;
providing a selected one of the first, second, third and fourth data signals by the output circuit at an output terminal.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/853,095Filed 29 Jun 2022 · continuation
Priority: 14 Jun 2019
Published: US 2022/0327275 A113 Oct 2022
Granted: 4 Jul 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
H03K 19/0948
Using MOSFET or insulated gate field-effect transistors, i.e. IGFET: using CMOS or complementary insulated gate field-effect transistors
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/39
Circuit design: circuit design at the physical level

Family

Application62/861,649Us provisional application · filed 14 Jun 2019
Application16/883,524Parent of this continuation · filed 26 May 2020
US 2022/0327275 A1Pre-grant publication · published 13 Oct 2022
US 11,392,743 B2Parent of this continuation
US 2020/0395938 A1Published application
US 11,694,012 B2This patent

From the US filing history. Foreign family members aren’t listed.