Reformatting scan patterns in presence of hold type pipelines
AssigneeSynopsys, Inc.
InventorsAmit Gopal M. Purohit, Sorin Ioan Popa, Denis Martin, Paras Chhabra
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Abstract
A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.
Claims20
A method comprising:
- identifying pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design;
- splitting, by a processor, each pattern of a plurality of patterns into a first part and a second part, wherein a length of the first part is a function of a number of the identified pipeline stages;
- and
- reformatting, by the processor, the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns.
A system comprising:
- a memory storing instructions;
- and
- a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
- identify pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design,
- split each pattern of a plurality of patterns into a first part and a second part, wherein a length of the first part is a function of a number of the identified pipeline stages, and
- reformat the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns in the another plurality of patterns.
A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
- identify pipeline stages in a pipeline path of a design for test of an integrated circuit design;
- split each pattern of a plurality of patterns into a first part and a second part, wherein a length of the first part is a function of a number of the identified pipeline stages;
- and
- reformat the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns.
Dependencies are inferred from the claim text.