Layered ready status reporting structure

A storage system comprising:

• a controller;
• a first storage device comprising a first ready/busy pin configured to output a first ready/busy signal carrying a first device identity (ID) and status information associated with the first storage device;
• a second storage device comprising a second ready/busy pin configured to output a second ready/busy signal carrying a second device ID and status information associated with the second storage device;
• a first shared data bus communicatively coupled between a first bridge device, the first storage device, and the second storage device;
• the first bridge device communicatively coupled between the controller, and the first ready/busy pin of the first storage device and the second ready/busy pin of the second storage device, the first bridge device being configured to aggregate the first ready/busy signal from the first ready/busy pin of the first storage device and the second ready/busy signal from the second ready/busy pin of the second storage device to transport to the controller;
• a third storage device;
• a fourth storage device;
• and
• a second bridge device communicatively coupled between the controller, and a third ready/busy pin of the third storage device and a fourth ready/busy pin of the fourth storage device, the second bridge device being configured to aggregate a third ready/busy signal from the third ready/busy pin of the third storage device and a fourth ready/busy signal from the fourth ready/busy pin of the fourth storage device to transport to the controller,
• wherein the first bridge device and the second bridge device are configured to communicate with the controller independently from each other, and
• wherein the first bridge device and the second bridge device are connected to the controller via a shared bus using a wire sharing protocol.

A method of encoding one or more plane identities (IDs) of one or more planes of a storage device, wherein memory of the storage device is divided into at least two planes, each of the at least two planes comprising a data register and a cache register, the method comprising:

• determining, by the storage device, if the one or more planes of the at least two planes of the storage device is available to perform one or more operations;
• based on determining that the one or more planes of the storage device is available to perform the one or more operations, turning, by the storage device, a ready/busy signal output from a ready/busy pin of the storage device to a first level and inserting one or more plane index codes associated with the one or more planes of the storage device in the ready/busy signal, wherein each of the plane index code is represented in form of a pulse and each of the plane index code follow a preamble bit;
• receiving, by a bridge device communicatively coupled between the ready/busy pin of the storage device and a controller, the ready/busy signal comprising the one or more plane index codes associated with the one or more planes of the storage device, from the storage device;
• decoding, by the bridge device, the one or more plane index codes associated with the one or more planes of the storage device;
• and
• reporting, by the bridge device, the decoded one or more plane index codes associated with the one or more planes of the storage device, to the controller,
• wherein the controller is configured to transmit/receive data to/from the storage device via the bridge device and a first shared data bus communicatively coupled between the bridge device and the storage device,
• wherein the storage device is configured to perform read or program operations concurrently on at least two pages, wherein each of the at least two planes of the storage device is configured to perform the read or the program operations to corresponding one of the at least two pages concurrently and independent of each other using the corresponding data register and the cache register, and
• wherein the ready/busy signal output from the ready/busy pin of the storage device is turned to the first level based on the at least two planes of the storage device being available to perform the read or the program operations on the data.