Multi-dimensional data path architecture
AssigneeArm Limited
InventorsPaul Nicholas Whatmough, Zhi-Gang Liu, Supreet Jeloka, Saurabh Pijuskumar Sinha, Matthew Mattina
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Abstract
Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.
Claims20
A device comprising:
- a multi-layered logic structure with a first logic layer and a second logic layer that are arranged vertically in a stacked configuration;
- a memory array that provides the same data to the first Iodic layer and the second logic layer by way of multiple data paths and a vertical inter-layer path;
- and
- an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure by way of the multiple data paths and the vertical inter-layer path,
- wherein the inter-layer data bus provides a first data path of the multiple data paths to the first logic layer, and
- wherein the inter-layer data bus provides a second data path of the multiple data paths and the vertical inter-layer path to the second logic layer for reuse of the same data provided by the memory array to the first logic layer.
A device comprising:
- a three-dimensional (3D) data reuse architecture with a master logic layer and a slave logic layer that are arranged vertically in a stacked configuration;
- a memory array that provides the same data to operands of the master logic layer and the slave logic layer;
- and
- an inter-layer data bus that vertically couples the master logic layer to slave logic layer, wherein the inter-layer data bus provides the operands to the slave logic layer for reuse of the same data provided by the memory array, and
- wherein the inter-layer data bus is arranged to provide the operands in a sequence from the master logic layer to the slave logic layer.
A device comprising:
- a three-dimensional (3D) data reuse architecture with a master logic layer and a slave logic layer that are arranged vertically in a stacked configuration;
- a memory array that provides the same data to operands of the master logic layer and the slave logic layer;
- and
- an inter-layer data bus that vertically couples the master logic layer to slave logic layer, wherein the master logic layer has a multiplier-accumulator that is shared with the slave logic layer for reuse of the same data provided to the operands of the master Iodic layer and the slave logic layer by the memory array.
Dependencies are inferred from the claim text.