Apparatuses and methods for cache operations
AssigneeMicron Technology, Inc.
InventorsJeremiah J. Willcock, Richard C. Murphy
Life of this patent
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Abstract
The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.
Claims20
An apparatus, comprising:
- first sensing circuitry that includes a sense amplifier and a compute component and is selectably coupled to a selected first subarray;
- and
- second sensing circuitry that includes a sense amplifier and does not include a compute component;
- wherein the second sensing circuitry is selectably coupled to a selected row of a selected second subarray in a memory device, wherein the second sensing circuitry is configured to sense a data value in the selected row of the selected second subarray;
- and
- wherein the memory device is configured to move the sensed data value to the first sensing circuitry to enable performance of a compute operation on the sensed data value using the compute component as a processing element to perform a compute operation on the sensed data value in the first sensing circuitry.
A system, comprising:
- a host configured to generate instructions executed to:
- provide a data value to either a first subset or a second subset of a plurality of subarrays of memory cells;
- and
- selectably move the data value between the first subset and the second subset based on whether a compute operation is to be performed on the data value, wherein the first subset comprises first sensing circuitry coupled thereto and the second subset comprises second sensing coupled thereto;
- and
- a cache controller configured to decode the instructions to move the data value from a subarray in the first subset to the second sensing circuitry coupled to the second subset to enable perform the compute operation on the data value;
- wherein the second sensing circuitry includes a sense amplifier and a compute component configured to perform compute operations;
- and
- wherein the first sensing circuitry includes a sense amplifier and does not include a compute component configured to perform compute operations.
A method, comprising:
- sensing a data value stored in a row of a first subarray in a memory device using first sensing circuitry, wherein the first sensing circuitry includes a sense amplifier, does not include a compute component, and is selectably coupled to the row of the first subarray;
- moving the sensed data value to second sensing circuitry coupled to a second subarray, wherein the sensing circuitry includes a sense amplifier and a compute component coupled thereto;
- and
- performing a compute operation on the sensed data value using the compute component.
Dependencies are inferred from the claim text.