Adaptive cache
AssigneeMicron Technologies, Inc.
InventorsDavid Andrew Roberts, Joseph Thomas Pawlowski
Life of this patent
Estimating the term…
Abstract
Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.
Claims18
An apparatus, comprising:
- a memory array configured as a plurality of hardware cache lines;
- and
- logic comprising a cache controller coupled to the plurality of hardware cache lines, the cache controller configured to:
- receive a parameter that indicates a cache line size;
- form, from the plurality of hardware cache lines, multiple cache lines having the cache line size indicated by the parameter, each cache line of the multiple cache lines comprising at least two of the hardware cache lines of the plurality of hardware cache lines;
- designate a tag of one of the at least two hardware cache lines of the cache line as a single tag;
- and
- disable or deactivate a tag of at least one other of the at least two hardware cache lines of the cache line.
A method, comprising:
- receiving a parameter that indicates a cache line size;
- forming multiple cache lines of a cache memory from hardware cache lines of the cache, each cache line of the multiple cache lines comprising a quantity of respective hardware cache lines, the quantity of hardware cache lines used to form each cache line based at least in part on the parameter that indicates the cache line size;
- associating, for at least one cache line of the multiple cache lines, the respective hardware cache lines from which the cache line is formed with a single tag, the associating:
- designating, for the at least one cache line of the multiple cache lines, a tag of one of the respective hardware cache lines from which the cache line is formed as the single tag of the cache line;
- and
- disabling or deactivating a tag of at least one other of the respective hardware cache lines from which the cache line is formed;
- and
- caching data of a backing memory within one or more of the multiple cache lines of the cache memory.
A system, comprising:
- a memory array configured as a cache comprising a plurality of hardware sets, each hardware set comprising hardware cache lines at respective set indexes;
- logic associated with the memory array and comprising a cache controller configured to:
- form the hardware cache lines into multiple cache lines having a specified size, the cache lines comprising respective hardware cache lines at same set indexes within two or more different hardware sets of the plurality of hardware sets;
- designate a tag of one of the respective hardware cache lines that form one of the cache lines of the multiple cache lines as a single tag of the one of the cache lines;
- disable or deactivate a tag of at least one other of the respective hardware cache lines that form the one of the cache lines of the multiple cache lines;
- and
- enable access to the one of the respective hardware cache lines that form the one of the cache lines of the multiple cache lines at least partially in parallel.
Dependencies are inferred from the claim text.