Error-handling flows in memory devices based on bins
AssigneeMicron Technology, Inc.
InventorsBruce A. Liikanen, Shane Nowell, Steven Michael Kientz
Life of this patent
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Abstract
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to detect a power-up state of the memory device following a power loss event; detect a read error with respect to data residing in a block of the memory device, wherein the block is associated with a current voltage offset bin; and perform temporal voltage shift (TVS)-oriented calibration for associating the block with a new voltage offset bin.
Claims20
A system comprising:
- a memory device comprising a plurality of blocks;
- and
- a processing device, operatively coupled to the memory device, performing the operations comprising:
- detecting a power-up state of the memory device following a power loss event;
- detecting a read error with respect to data residing in two or more blocks of the plurality of blocks of the memory device, wherein each of the plurality of blocks is associated with a respective current voltage offset bin of a plurality of voltage offset bins, wherein each voltage offset bin of the plurality of voltage offset bins is associated with a respective predefined voltage offset value;
- and
- re-synchronizing the two or more blocks by performing temporal voltage shift (TVS)-oriented calibration for associating each of the two or more blocks with a respective new voltage offset bin of the plurality of voltage offset bins, wherein the two or more blocks are re-synchronized in reverse order of recency of the voltage offset bins to compensate for difference in respective accumulated voltage offsets over time.
A method comprising:
- determining a respective current voltage offset bin associated with each block of a plurality of blocks of a memory device, wherein the respective current voltage offset bin is one of a plurality of voltage offset bins, wherein each voltage offset bin of the plurality of voltage offset bins is associated with a respective predefined voltage offset value;
- detecting a power-up state of the memory device following a power loss event;
- and
- initiating a re-synchronization process to avoid read error with respect to data residing in two or more blocks of the plurality of blocks of the memory device, wherein the re-synchronization process performs temporal voltage shift (TVS)-oriented calibration for associating each of the two or more blocks with a respective new voltage offset bin of the plurality of voltage offset bins, wherein the two or more blocks are re-synchronized in reverse order of recency of the voltage offset bins to compensate for difference in respective accumulated voltage offsets over time.
A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:
- detecting a power-up state of the memory device following a power loss event, wherein the memory device comprises a plurality of blocks;
- detecting a read error with respect to data residing in two or more blocks of the plurality of blocks of the memory device, wherein each block of the plurality of blocks is associated with a respective current voltage offset bin of a plurality of voltage offset bins, wherein each voltage offset bin of the plurality of voltage offset bins is associated with a respective predefined voltage offset value;
- and
- re-synchronizing the two or more blocks by performing temporal voltage shift (TVS)-oriented calibration for associating each of the two or more blocks with a respective new voltage offset bin of the plurality of voltage offset bins, wherein the two or more blocks are re-synchronized in reverse order of recency of the voltage offset bins to compensate for difference in respective accumulated voltage offsets over time.
Dependencies are inferred from the claim text.