Method of completing a programmable atomic transaction by ensuring memory locks are cleared
AssigneeMicron Technology, Inc.
InventorTony Brewer
Life of this patent
Estimating the term…
Abstract
Disclosed is an instruction for a programmable atomic transaction that is executed as the last instruction and that terminates the executing thread, waits for all outstanding store operations to finish, clears the programmable atomic lock, and sends a completion response back to the issuing process. This guarantees that the programmable atomic lock is cleared when the transaction completes. By coupling thread termination with clearing the lock bit, this guarantees that the thread cannot terminate without clearing the lock.
Claims20
An apparatus, comprising:
- a memory array;
- a memory controller coupled to the memory array, the memory controller comprising an internal memory storing a lock data structure for controlling access to one or more memory locations of the memory array;
- a programmable atomic unit coupled to the memory controller and comprising:
- an instruction memory, configured to store one or more instruction sets;
- and
- a processor, the processor configured to:
- receive a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in the instruction memory;
- set a lock in the lock data structure of the internal memory of the memory controller for a portion of the memory array, the lock preventing subsequent access to the portion of the memory array, the lock set by adding a data structure to a table of linked lists indexed using a hash of a memory address of the portion of the memory array;
- execute the instruction set;
- and
- execute an instruction to terminate the execution of the instruction set, the instruction to terminate the execution of the instruction set comprising an operation to clear the lock, the lock cleared by removing the data structure added to the table of linked lists indexed using a hash of the memory address of the portion of the memory array.
A method, comprising:
- at a programmable atomic unit coupled to a memory controller and including a processor:
- receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in a memory of the programmable atomic unit;
- setting a lock in a lock data structure of an internal memory of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller, the lock set by adding a data structure to a table of linked lists indexed using a hash of a memory address of the portion of the memory array;
- executing the instruction set;
- and
- executing an instruction to terminate the execution of the instruction set, the instruction to terminate the execution of the instruction set comprising an operation to clear the lock, the lock cleared by removing the data structure added to the table of linked lists indexed using a hash of the memory address of the portion of the memory array.
A non-transitory machine-readable medium, storing instructions, which when executed by a machine causes the machine to perform operations comprising:
- receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in a memory of a programmable atomic unit;
- setting a lock in a lock data structure of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller, the lock set by adding a data structure to a table of linked lists indexed using a hash of a memory address of the portion of the memory array;
- executing the instruction set;
- and
- executing an instruction to terminate the execution of the instruction set, the instruction to terminate the execution of the instruction set comprising an operation to clear the lock, the lock cleared by removing the data structure added to the table of linked lists indexed using a hash of the memory address of the portion of the memory array.
Dependencies are inferred from the claim text.