US 11,693,665 B2Granted

Co-scheduled loads in a data processing apparatus

AssigneeArm Limited

InventorsMbou Eyole, Michiel Willem Van Tol

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Abstract

A data processing apparatus and method of operating such is disclosed. Issue circuitry buffers operations prior to execution until operands are available in a set of registers. A first and a second load operation are identified in the issue circuitry, when both are dependent on a common operand, and when the common operand is available in the set of registers. Load circuitry has a first address generation unit to generate a first address for the first load operation and a second address generation unit to generate a second address for the second load operation. An address comparison unit compares the first address and the second address. The load circuitry is arranged to cause a merged lookup to be performed in local temporary storage, when the address comparison unit determines that the first and the second address differ by less than a predetermined address range characteristic of the local temporary storage.

Claims24

Dependent claims

A data processing apparatus comprising:

execution circuitry to perform data processing operations m response to a sequence of instructions;
issue circuitry to buffer operations resulting from the sequence of instructions prior to execution until operands required by the operations are available in a set of registers, wherein the issue circuitry is arranged to identify a first load operation and a second load operation based on the first load operation and the second load operation being dependent on a common operand and an availability of the common operand in the set of registers;
load circuitry to load at least one operand into the set of registers in response to a load instruction in the sequence of instructions, wherein the load circuitry further comprises:
a first address generation unit arranged to generate a first address in response to the first load operation identified by the issue circuitry;
a second address generation unit arranged to generate a second address in response to the second load operation identified by the issue circuitry;
and
an address comparison unit arranged to compare the first address and the second address;
and
local temporary storage to store copies of data values from memory, wherein the load circuitry is arranged to cause a merged lookup to be performed in the local temporary storage based on the first address and the second address when the address comparison unit determines that the first address and the second address differ by less than a predetermined address range characteristic of the local temporary storage.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/754,739Filed 28 Sep 2020
Priority: GB 191492315 Oct 2019
Published: US 2023/0064455 A12 Mar 2023
Granted: 4 Jul 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/30043
To perform operations on memory: lOAD or STORE instructions; Clear instruction
G06F 9/30181
Arrangements for executing machine instructions, e.g. instruction decode: instruction operation extension or modification
G06F 9/345
Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes: of multiple operands or results