Methods for performing fused-multiply-add operations on serially allocated data within a processing-in-memory capable memory device, and related memory devices and systems

A system, comprising:

• at least one memory array and configured to:
• serially load, via a first bit line, a first number of bits from a first group of bits into a sequencer coupled to the first bit line;
• load, to circuitry adjacent to the at least one memory array and via one or more second, different dedicated bit lines, a second number of bits from a second group of bits;
• perform, at the circuitry, one or more operations on the first number of bits or the second number of bits, or both;
• and
• store a result of the one or more operations to the at least one memory array.

A system, comprising:

• at least one input device;
• at least one output device;
• at least one processor device coupled to the at least one input device and the at least one output device;
• and
• at least one memory device coupled to the at least one processor device and comprising:
• a memory cell array;
• and
• logic coupled to the memory cell array and configured to perform fused-multiply-add operations, including:
• serially receiving, via a bit line, an input vector;
• serially reading, via one or more different, dedicated bit lines, a number of bits of a group of bits of a first matrix, the one or more different, dedicated bit lines parallel to the bit line;
• multiplying the number of bits of the group of bits of the first matrix by the input vector to generate an intermediate group of bits;
• serially receiving, via the bit line, at least one additional input vector;
• serially reading, via the one or more different, dedicated bit lines, a number of bits of at least one additional group of bits of the first matrix;
• multiplying the number of bits of the at least one additional group of bits by the at least one additional input vector to update the intermediate group of bits;
• and
• generating an output based on the intermediate group of bits.