Compiler program, compiling method, information processing device

A method of compiling that executes optimization processing for an optimization target program,

• the optimization processing comprising:
• the optimization target program including a loop including a vector store instruction and a vector load instruction for an array variable,
• unrolling the vector store instruction and the vector load instruction in the loop by an unrolling number of times to generate a plurality of unrolled vector store instructions and a plurality of unrolled vector load instructions, the unrolling number of times including a first unrolling number of times, which is obtained by dividing a vector length by an array size of the array variable and rounding up a remainder, or a second unrolling number of times lower than the first unrolling number of times by one;
• and
• scheduling to move an unrolled vector load instruction among the plurality of unrolled vector load instructions, which is located after a first unrolled vector store instruction that is located at first among the plurality of unrolled vector load instructions, before the first unrolled vector store instruction.

An information processing device comprising:

• a processor;
• a memory accessed by the processor,
• wherein the processor executes optimization processing for an optimization target program,
• the optimization target program including a loop including a vector store instruction and a vector load instruction for an array variable, and
• the optimization processing including:
• unrolling the vector store instruction and the vector load instruction in the loop by an unrolling number of times to generate a plurality of unrolled vector store instructions and a plurality of unrolled vector load instructions, the unrolling number of times including a first unrolling number of times, which is obtained by dividing a vector length by an array size of the array variable and rounding up a remainder, or a second unrolling number of times lower than the first unrolling number of times by one;
• and
• scheduling to move an unrolled vector load instruction among the plurality of unrolled vector load instructions, which is located after a first unrolled vector store instruction that is located at first among the plurality of unrolled vector load instructions, before the first unrolled vector store instruction.