Methods and apparatus to detect and annotate backedges in a dataflow graph
AssigneeIntel Corporation
InventorsKermin E. ChoFleming, Jr., Jesmin Jahan Tithi, Joshua Cranmer, Suresh Srinivasan
Life of this patent
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Abstract
Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
Claims24
An apparatus to optimize hardware execution efficiency, the apparatus comprising:
- backedge identifier circuitry to identify a backedge of a data flow graph, the data flow graph representative of input code;
- buffer inserter circuitry to:
- determine an optimization goal for the data flow graph based on a resource characteristic of a configurable spatial accelerator;
- and
- insert a quantity of buffers into the data flow graph, the quantity of buffers based on the optimization goal;
- and
- compiler circuitry to generate output code based on the data flow graph.
An apparatus to optimize hardware execution efficiency, the apparatus comprising:
- backedge identifier circuitry to identify a backedge of a data flow graph, the data flow graph representative of input code;
- buffer inserter circuitry to:
- determine a critical path latency of the data flow graph associated with the backedge, the critical path having a longer latency relative to a second path also associated with the backedge;
- determine an optimization goal for the data flow graph based on a resource characteristic of target hardware circuitry;
- and
- insert a quantity of buffers into the data flow graph based on:
- (a) the optimization goal, and (b) a comparison of the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency associated with the second path;
- and
- compiler circuitry to generate output code based on the data flow graph.
At least one non-transitory machine-readable medium comprising instructions that, when executed, cause at least one processor to at least:
- identify a backedge of a data flow graph, the data flow graph representative of input code;
- determine an optimization goal for the data flow graph based on a resource characteristic of a configurable spatial accelerator;
- insert a quantity of buffers into the data flow graph, the quantity of buffers based on the optimization goal;
- and
- generate output code based on the data flow graph.
At least one non-transitory machine readable medium comprising instructions that, when executed, cause at least one processor to at least:
- identify a backedge of a data flow graph, the data flow graph representative of input code;
- determine a critical path latency of the data flow graph associated with the backedge, the critical path having a longer latency relative to a second path also associated with the backedge;
- determine an optimization goal for the data flow graph based on a resource characteristic of target hardware circuitry;
- insert a quantity of buffers into the data flow graph based on:
- (a) the optimization goal, and (b) a comparison of the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency associated with the second path;
- and
- generate output code based on the data flow graph.
A method to optimize hardware execution efficiency, the method comprising:
- identifying a backedge of a data flow graph, the data flow graph representative of input code;
- determining an optimization goal for the data flow graph based on a resource characteristic of a configurable spatial accelerator;
- and
- inserting a quantity of buffers into the data flow graph, the quantity of buffers based on the optimization goal;
- and
- generating output code based on the data flow graph.
A method to optimize hardware execution efficiency, the method comprising:
- identifying a backedge of a data flow graph, the data flow graph representative of input code:
- determining a critical path latency of the data flow graph associated with the backedge, the critical path having a longer latency relative to a second path also associated with the backedge;
- determining an optimization goal for the data flow graph based on a resource characteristic of target hardware circuitry;
- inserting a quantity of buffers into the data flow graph based on:
- (a) the optimization goal, and (b) a comparison of the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency associated with the second path;
- and
- generating output code based on the data flow graph.
An apparatus to optimize hardware execution efficiency, the apparatus comprising:
- means for identifying a backedge of a data flow graph, the data flow graph representative of input code;
- means for inserting buffers to:
- determine a critical path latency of the data flow graph associated with the backedge, the critical path having a longer latency relative to a second path also associated with the backedge;
- determine an optimization goal for the data flow graph based on a resource characteristic of target hardware circuitry;
- and
- insert a quantity of buffers into the data flow graph, the quantity of buffers based on:
- (a) the optimization goal, and (b) a comparison of the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency associated with the second path;
- and
- means for generating output code based on the data flow graph.
Dependencies are inferred from the claim text.