Storage device including nonvolatile memory device and controller, controller and operating method of nonvolatile memory device

A storage device comprising:

• a nonvolatile memory including a plurality of nonvolatile memory cells;
• and
• a controller comprising:
• a host interface configured to communicate with an external host device;
• a memory interface including a direct memory access (DMA) configured to convey a command, an address, and data to the nonvolatile memory through an input/output channel;
• a memory including a command queue and storing computer-executable instructions;
• an error correction block configured to perform error correction encoding based on the data being written in the nonvolatile memory, and perform error correction decoding on the data being received from the nonvolatile memory;
• and
• processing circuitry including a first processor configured for communication with the host and a second processor configured for communication with the nonvolatile memory, the processing circuitry being configured to execute the computer-executable instructions so as to:
• communicate with an external host device through the host interface,
• communicate with the nonvolatile memory through the memory interface,
• communicate with a random access memory through a buffer control circuit,
• enqueue first write commands and first read commands received from the external host device in the command queue,
• slice at least one write command of the first write commands to generate a plurality of sub-commands, and
• fetch a command from the command queue and alternately transmit at least one read command of the first read commands, and one sub-command of the plurality of sub-commands to the nonvolatile memory through the DMA, the alternately transmitting the at least one read command and the one sub-command including performing the alternating when the respective queues are not empty.

A controller comprising:

• a host interface configured to communicate with an external host device;
• a memory interface including a direct memory access (DMA) configured to convey a command, an address, and data to a nonvolatile memory through an input/output channel;
• a memory including a command queue and storing computer-executable instructions;
• an error correction block configured to perform error correction encoding based on the data being written in the nonvolatile memory, and perform error correction decoding on the data being received from the nonvolatile memory;
• and
• processing circuitry including a first processor configured for communication with the host interface and a second processor configured for communication with the nonvolatile memory, the processing circuitry configured to execute the computer-executable instructions so as to:
• communicate with the external host device through the host interface,
• communicate with the nonvolatile memory through the memory interface,
• communicate with a random access memory through a buffer control circuit,
• enqueue first write commands and first read commands received from the external host device in the command queue,
• slice at least one write command of the first write commands to generate a plurality of sub-commands, the slicing set to an integer multiple of one of a translation unit of a translation layer, a write unit of the nonvolatile memory, or an access unit of the DMA, and
• fetch a command from the command queue and alternately transmit at least one read command of the first read commands, and one sub-command of the plurality of sub-commands to the nonvolatile memory through the DMA.