Memory system managing number of read operations using two counters
AssigneeKioxia Corporation
InventorsSuguru Nishikawa, Yoshihisa Kojima, Takehiko Amaki
Life of this patent
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AssigneeKioxia Corporation
InventorsSuguru Nishikawa, Yoshihisa Kojima, Takehiko Amaki
Estimating the term…
A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.
A memory system comprising:
A memory system comprising:
A method of controlling a nonvolatile memory that includes a memory cell array including a plurality of first units and at least one second unit, the second unit including the plurality of first units, the plurality of first units including at least a third unit, the method comprising:
Dependencies are inferred from the claim text.