Address hashing in a multiple memory controller system

A method comprising:

• generating a memory request having a first address in a memory address space that is mapped to memory devices in a system having a plurality of memory controllers, wherein:
• a given memory address in the memory address space uniquely identifies a memory location in one of the memory devices coupled to one of the plurality of memory controllers,
• a given page within the memory address space is divided into a plurality of blocks, and
• the plurality of blocks of the given page are distributed over two or more of the plurality of memory controllers;
• hashing sets of address bits from the first address to direct the memory request to a first memory controller of the plurality of memory controllers, wherein the sets of address bits locate the first memory controller at a plurality of levels of granularity, and wherein a first subset of the address bits are hashed for a first level of the plurality of levels of granularity and a second subset of the address bits are hashed corresponding to a second level of the plurality of levels of granularity, and wherein a bit position within the first memory address of at least one address bit in the first subset differs from the bit positions of the address bits in the second subset;
• and
• routing the memory request to the first memory controller based on the hashing.

A system comprising:

• a plurality of memory controllers configured to control access to memory devices, wherein the plurality of memory controllers are physically distributed over one or more integrated circuit die in the system, wherein a location of a given memory controller is identified by which of a plurality of slices within the integrated circuit die includes the given memory control, which of a plurality of rows within a given slice of the plurality of slices includes the given memory controller, and which of a plurality of sides of a given row of the plurality of rows includes the memory controller;
• a plurality of hardware agents configured to access data in the memory devices using memory addresses, wherein:
• the memory addresses are defined within a memory address space that maps memory addresses to memory locations in the memory devices, and
• a given memory address in the memory address space uniquely identifies a memory location in one of the memory devices coupled to one of the plurality of memory controllers,
• a given page within the memory address space is divided into a plurality of blocks, and
• the plurality of blocks of the given page are distributed over the plurality of memory controllers;
• and
• a communication fabric coupled to the plurality of memory controllers and the plurality of hardware agents, wherein:
• the communication fabric is configured to route a memory request having a first memory address to a first memory controller of the plurality of memory controllers based on the first memory address, and
• address bits of the first memory address are hashed to determine a first slice of the plurality of slices, a first row of the plurality of rows, and a first side of the plurality of sides that includes the first memory controller, wherein a first subset of address bits are hashed to determine the first slice, a second subset of address bits are hashed to determine the first row, and a third subset of address bits are hashed to determine the first side, and wherein a bit position within the first memory address of at least one address bit in the first subset differs from the bit positions of the address bits in the second subset and the third subset.