US 11,693,584 B2Granted

Word line control method, word line control circuit device and semiconductor memory

AssigneeChangxin Memory Technologies, Inc.

InventorLiang Zhang

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Abstract

A word line control method, a word line control circuit device, and a semiconductor memory are provided. The method includes: acquiring a row address input signal; acquiring a test mode signal; performing logical and decoding operations on the row address input signal and the test mode signal to generate a row address control signal, wherein the row address control signal includes at least two valid activation signals; and simultaneously activating at least two non-adjacent word lines based on the at least two valid activation signals. The row address control signal obtained allows simultaneous activation of at least two non-adjacent word lines. Since none of any two non-adjacent word lines share a common contact area, a test will not be affected by the disconnection of a contact area or the presence of high impedance, thus improving test accuracy.

Claims10

Dependent claims

A word line control method for a word line control circuit device, wherein the word line control circuit device comprises a test mode input circuit, a row address input circuit, and a logic decoding processor, wherein the test mode input circuit comprises a first inverter, wherein the row address input circuit comprises a second inverter, wherein the logic decoding processor comprises a first NAND gate, a second NAND gate, and a decoding device, and wherein the word line control method comprising:

acquiring a row address input signal by the row address input circuit;
acquiring a test mode signal by the test mode input circuit;
performing logical and decoding operations on the row address input signal and the test mode signal by the logic decoding processor to generate a row address control signal, wherein the row address control signal includes at least two valid activation signals;
and
simultaneously activating at least two non-adjacent word lines by the logic decoding processor based on the at least two valid activation signals,
wherein the row address input signal includes a plurality of row address signals, and wherein performing logical and decoding operations on the row address input signal and the test mode signal to generate a row address control signal comprises:
performing an inverse operation by the first inverter on the test mode signal to generate an inverted test signal;
selecting one of the plurality of row address signals, and performing a NAND operation on the selected row address signal and the inverted test signal by the first NAND gate to generate an inverted output row address;
performing inverse operations by the second inverter on all the row address signals to generate corresponding inverted row address signals;
performing a NAND operation on the inverted row address signal corresponding to the selected row address signal and the inverted test signal by the second NAND gate to generate a non-inverted output row address;
and
decoding the inverted output row address, the non-inverted output row address, unselected row address signals and unselected inverted row address signals by the decoding device to obtain the row address control signal.

9 more elements

A word line control circuit device, comprising:

a test mode input circuit, configured to receive a test mode signal;
a row address input circuit, configured to receive a plurality of row address signals;
and
a logic decoding processor, configured to perform logical and decoding operations on the plurality of row address signals and the test mode signal to generate a row address control signal, wherein the row address control signal includes at least two valid activation signals, configured for simultaneously activating at least two non-adjacent word lines,
wherein the test mode input circuit has an output coupled, together with an output of the row address input circuit, to a signal input of the logic decoding processor,
wherein the logic decoding processor has a signal output coupled to a plurality of word lines in a memory array,
wherein the test mode input circuit comprises:
a test mode input, configured to receive the test mode signal;
a first inverter, configured to perform an inverse operation on the test mode signal to generate an inverted test signal;
and
a test mode output, configured to output the inverted test signal,
wherein the row address input circuit comprises:
a plurality of row address signal lines, configured to receive the corresponding one of the row address signals from the row address input signal, respectively;
and
a plurality of second inverters coupled to the corresponding one of the row address signal lines, respectively, and configured to perform inverse operations on the row address signals to generate a plurality of inverted row address signals,
and wherein the logic decoding processor comprises:
a first NAND gate, configured to perform a NAND operation on the selected one of the row address signals and the inverted test signal to generate an inverted output row address;
a second NAND gate, configured to perform a NAND operation on one of the inverted row address signals corresponding to the selected row address signal and the inverted test signal to generate a non-inverted output row address;
and
a decoding device, configured to decode the inverted output row address, the non-inverted output row address, unselected row address signals and unselected inverted row address signals to obtain the row address control signal,
wherein the first NAND gate includes a first input coupled to the one of the row address signal lines corresponding to the selected row address signal, a second input coupled to the test mode output and configured to receive the inverted test signal, and a first output,
and wherein the second NAND gate includes a third input coupled to an output of one of the second inverters corresponding to the selected row address signal, a fourth input coupled to the test mode output, and a second output.

19 more elements

A semiconductor memory comprising a word line control circuit device, wherein the word line control circuit device comprises:

a test mode input circuit, configured to receive a test mode signal;
a row address input circuit, configured to receive a plurality of row address signals;
and
a logic decoding processor, configured to perform logical and decoding operations on the plurality of row address signals and the test mode signal to generate a row address control signal, wherein the row address control signal includes at least two valid activation signals, configured for simultaneously activating at least two non-adjacent word lines,
wherein the test mode input circuit has an output coupled, together with an output of the row address input circuit, to a signal input of the logic decoding processor,
wherein the logic decoding processor has a signal output coupled to a plurality of word lines in a memory array,
wherein the test mode input circuit comprises:
a test mode input, configured to receive the test mode signal;
a first inverter, configured to perform an inverse operation on the test mode signal to generate an inverted test signal;
and
a test mode output, configured to output the inverted test signal,
wherein the row address input circuit comprises:
a plurality of row address signal lines, configured to receive the corresponding one of the row address signals from the row address input signal, respectively;
and
a plurality of second inverters coupled to the corresponding one of the row address signal lines, respectively, and configured to perform inverse operations on the row address signals to generate a plurality of inverted row address signals,
and wherein the logic decoding processor comprises:
a first NAND gate, configured to perform a NAND operation on the selected one of the row address signals and the inverted test signal to generate an inverted output row address;
a second NAND gate, configured to perform a NAND operation on one of the inverted row address signals corresponding to the selected row address signal and the inverted test signal to generate a non-inverted output row address;
and
a decoding device, configured to decode the inverted output row address, the non-inverted output row address, unselected row address signals and unselected inverted row address signals to obtain the row address control signal, wherein the row address control signal includes the at least two valid activation signals,
wherein the first NAND gate includes a first input coupled to the one of the row address signal lines corresponding to the selected row address signal, a second input coupled to the test mode output and configured to receive the inverted test signal, and a first output,
and wherein the second NAND gate includes a third input coupled to an output of one of the second inverters corresponding to the selected row address signal, a fourth input coupled to the test mode output, and a second output.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/171,307Filed 9 Feb 2021 · continuation
Priority: CN 201811351053.214 Nov 2018
Published: US 2021/0165602 A13 Jun 2021
Granted: 4 Jul 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 3/0655
Making use of a particular technique: vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more…
G06F 3/0604
Specifically adapted to achieve a particular effect: improving or facilitating administration, e.g. storage management
G06F 3/0679
Single storage device: non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
G11C 29/025
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in signal lines