Automatic read calibration operations
AssigneeIntel Corporation
InventorsAliasgar S. Madraswala, Ali Khakifirooz, Camila Jaramillo, John Egler, Netra Mahuli, Renjie Chen, Yogesh Wakchaure
Life of this patent
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Abstract
An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.
Claims20
An apparatus comprising:
- a plurality of memory cells;
- a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells;
- and
- a controller to:
- transpose a value indicative of a voltage of the first cell to the sense node;
- isolate the sense node from the bitline;
- calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter;
- and
- store the calibrated parameter and apply the calibrated parameter in a subsequent read operation.
A method comprising:
- transposing a value indicative of a voltage of a first memory cell to a sense node of a sense circuit;
- isolating the sense node from a bitline selectively coupled to the first memory cell;
- calibrating a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter;
- and
- storing, by a controller, the calibrated parameter and applying, by the controller, the calibrated parameter in a subsequent read operation.
A storage device comprising:
- a storage device controller;
- and
- a plurality of memory chips, wherein a memory chip comprises:
- a plurality of memory cells;
- a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells;
- and
- a memory chip controller to:
- transpose a value indicative of a voltage of the first cell to the sense node;
- isolate the sense node from the bitline;
- calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter;
- and
- store the calibrated parameter and apply the calibrated parameter in a subsequent read operation.
Dependencies are inferred from the claim text.