Apparatuses and methods for memory alignment
AssigneeMicron Technology, Inc.
InventorJohn D. Leidel
Life of this patent
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Abstract
The present disclosure includes apparatuses and methods related to memory alignment. An example method comprises performing an alignment operation on a first byte-based memory element and a second byte-based memory element such that a padding bit of the first byte-based memory element is logically adjacent to a padding bit of the second byte-based memory element and a data bit of the first byte-based memory element is logically adjacent to a data bit of the second byte-based memory element.
Claims20
A method for memory alignment, comprising:
- translating a logical address for data to a physical address for the data based on:
- a quantity of data bits of each of a plurality of memory elements of the data;
- a quantity of padding bits of each of the plurality of memory elements;
- a quantity of memory elements of the data;
- and
- a value equivalent to the quantity of padding bits multiplied by the quantity of memory elements;
- and
- performing a logical operation, via sensing circuitry, on the data at the physical address.
An apparatus, comprising:
- a controller configured to:
- cause a logical address for data of a memory allocation to be translated to a physical address for the data based on:
- a quantity of data bits of each memory element of the memory allocation;
- a quantity of padding bits of each memory elements of the memory allocation;
- and
- a quantity of memory elements from a start of the memory allocation to the logical address;
- and
- cause the logical address to be adjusted by a value equivalent to the quantity of padding bits multiplied by the quantity of memory elements from the start of the memory allocation to the logical address.
A non-transitory machine-readable medium storing instructions executable by a processing resource to:
- translate a logical address for data of a first memory element of a memory allocation to a physical address of a memory device at which the data is stored based on:
- a quantity of data bits of the first memory element;
- a quantity of padding bits of the first memory element;
- and
- a quantity of memory elements from a start of the memory allocation to the logical address;
- and
- store a plurality of memory elements of the memory allocation according to a non-byte-based alignment,
- wherein in the non-byte-based alignment at least one data bit of the first memory element and at least one data bit of a second memory element of the memory allocation are logically adjacent at a location of the memory allocation other than a byte boundary and stored in physically adjacent memory cells of the array.
Dependencies are inferred from the claim text.