Memory performance optimization method, memory control circuit unit and memory storage device

A memory control circuit unit for controlling a memory storage device comprising a rewritable non-volatile memory module, wherein the memory control circuit unit comprises:

• a host interface configured to couple to a host system;
• a memory interface configured to couple to the rewritable non-volatile memory module;
• a buffer memory;
• and
• a memory management circuit coupled to the host interface, the memory interface, and the buffer memory,
• wherein the memory management circuit is configured to count an idle time of the memory storage device in an active mode,
• the memory management circuit is further configured to instruct the memory storage device to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold,
• the memory management circuit is further configured to count a first waiting time of the memory storage device in the first low electricity consumption mode,
• the memory management circuit is further configured to instruct the memory storage device to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold, wherein electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode,
• the memory management circuit is further configured to:
• count a second waiting time of the memory storage device in the first low electricity consumption mode in response to a condition for performing a background operation being met;
• instruct the memory storage device to enter a background mode from the first low electricity consumption mode in response to the second waiting time being greater than a second waiting threshold;
• instruct the memory storage device to enter the first low electricity consumption mode from the background mode after the background operation being performed, and count a third waiting time of the memory storage device in the first low electricity consumption mode;
• and
• instruct the memory storage device to enter the second low electricity consumption mode from the first low electricity consumption mode in response to the third waiting time being greater than a third waiting threshold, wherein the third waiting threshold is equal to the first waiting threshold minus the second waiting threshold.

A memory storage device comprising:

• a connection interface unit configured to couple to a host system;
• a rewritable non-volatile memory module;
• and
• a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit comprises a buffer memory,
• wherein the memory control circuit unit is configured to count an idle time of the memory storage device in an active mode,
• the memory control circuit unit is further configured to instruct the memory storage device to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold,
• the memory control circuit unit is further configured to count a first waiting time of the memory storage device in the first low electricity consumption mode,
• the memory control circuit unit is further configured to instruct the memory storage device to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold, wherein electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode,
• the memory control circuit unit is further configured to:
• count a second waiting time of the memory storage device in the first low electricity consumption mode in response to a condition for performing a background operation being met;
• instruct the memory storage device to enter a background mode from the first low electricity consumption mode in response to the second waiting time being greater than a second waiting threshold;
• instruct the memory storage device to enter the first low electricity consumption mode from the background mode after the background operation being performed, and count a third waiting time of the memory storage device in the first low electricity consumption mode;
• and
• instruct the memory storage device to enter the second low electricity consumption mode from the first low electricity consumption mode in response to the third waiting time being greater than a third waiting threshold, wherein the third waiting threshold is equal to the first waiting threshold minus the second waiting threshold.