SRAM-based cell for in-memory computing and hybrid computations/storage memory architecture

A computing device, comprising:

• a plurality of input lines;
• a plurality of output lines;
• a plurality of control signal generators;
• a plurality of currenet control lines, each connected to a respective one of the plurality of control signal generators, and
• a plurality of memory cells logically arranged in a two-dimensional array of rows, each associated with a respective one of the plurality of input lines, and columns, each associated with a respective one of the output lines and the current control lines, each of the memory cell including:
• a memory unit having at least two memory states;
• a first switching transistor adapted to receive from the memory unit a signal indicative of the memory state and be on or off at least in part depending on the memory state,
• a second switching transistor adapted to receive from the input line associated with the memory cell an input signal and adapted to be on or off at least in part depending on the input signal, and
• a current regulating transistor adapted to receive via the current control line associated with the memory cell a control signal from the control signal generator associated with the memory cell and generate a current at a level at least in part depending on the control signal,
• the first and second switching transistors and the current regulating transistor being connected to pass to the output line the current of the level determined by a combination of the memory state, the input signal and the control signal,
• wherein the levels of currents generated by at least two of the respective current regulating transistors are different from each other, and
• wherein each of the memory states corresponds to a numerical weight value, and the input signal corresponds to a numerical input value, wherein the first and second switching transistors and the current regulating transistor are connected to pass to the output line the current of the level proportional to a product the numerical weight value corresponding to the memory state and the numerical input value corresponding to the input signal.

A method of computing, comprising:

• storing a plurality of digits of a multi-digit number, each of the digits having a value and a place value, in a plurality of respective memory elements;
• turning on or off a plurality of current sources, each associated with a respective one of the memory elements, depending on the value of the digit stored in the respective memory element;
• applying a control signal to each of the current sources to set a level of current the respective current source is to supply according to the place value of the digit stored in the respective memory element, wherein the levels of currents set for at least two of the respective current sources are different from each other;
• and
• applying an input signal through an input line to activate a plurality of switch devices, each associated with a respective one of the memory elements, to permit flow of the current supplied by the respective current source to an output line associated with the memory element,
• wherein the applying an input signal comprising applying a train of a plurality of pulses having a pulse count, or a single pulse having a pulse width, and obtaining from the current supplied to the output line a quantity that is proportional to a product of the pulse count or pule width and the stored multi-digit number.