Multi-die power management in SoCs

A system comprising:

• an integrated circuit;
• a plurality of voltage regulators configured to supply a plurality of supply voltages to the integrated circuit;
• a plurality of power delivery trigger circuits coupled to the integrated circuit and the plurality of voltage regulators, wherein the power delivery trigger circuits are configured to monitor the plurality of voltage regulators and generate a plurality of trigger signals based on electrical load experienced by the plurality of voltage regulators;
• wherein the integrated circuit comprises:
• a plurality of components configured to generate memory transactions to access memory;
• and
• a plurality of memory controller circuits configured to control the memory;
• and
• a trigger logic circuit coupled to the plurality of power delivery trigger circuits, wherein the trigger logic circuit is configured to generate a power reduction signal based on the plurality of trigger signals received from the plurality of power delivery trigger circuits;
• wherein a given memory controller circuit of the plurality of memory controller circuits comprises a plurality of rate limiter circuits at a plurality of locations in a pipeline within the given memory controller circuit, and wherein one or more of the plurality of rate limiter circuits is configured to limit a rate at which memory transactions flow through the plurality of locations.

A method comprising:

• receiving, at an integrated circuit, a plurality of supply voltages from a plurality of voltage regulators, wherein the integrated circuit includes a plurality of components that generate memory transactions to access memory, a plurality of memory controller circuits that control the memory, and a communication fabric comprising a plurality of circuits that interconnect the plurality of components and the plurality of memory controller circuits;
• generating, by a plurality of power delivery trigger circuits coupled to the integrated circuit and the plurality of voltage regulators, a plurality of trigger signals based on electrical load experienced by the plurality of voltage regulators;
• generating, at a trigger logic circuit coupled to the plurality of power delivery trigger circuits, a power reduction signal based on the plurality of trigger signals received from the plurality of power delivery trigger circuits;
• controlling, by a rate control circuit coupled to at least one of the plurality of power delivery trigger circuits, a clock rate for the plurality of circuits in the communication fabric, wherein the clock rate is reduced based on at least one of the plurality of trigger signals from the at least one of the power delivery trigger circuits;
• and
• controlling, by a given memory controller circuit of the plurality of memory controller circuits, a rate at which memory transactions flow through a plurality of locations according to a plurality of rate limiter circuits at a plurality of locations in a pipeline within the given memory controller circuit.