Module reset circuit, reset unit and SoC reset architecture

A method, comprising:

• receiving, at a signal receiving circuit, a reset configuration signal from an exceptional timing sequence device in a functional module;
• outputting, by the signal receiving circuit, a trigger signal;
• generating, at a first signal generation circuit that is electrically connected to the signal receiving circuit, an idle signal based at least in part on the trigger signal, wherein:
• the idle signal is used to configure a shutdown signal;
• and
• the shutdown signal is used to shut down a first clock signal of the exceptional timing sequence device and a second clock signal in a same clock domain as the first clock signal of the exceptional timing sequence device;
• generating, at a second signal generation circuit that is electrically connected to the signal receiving circuit, a reset enable signal based at least in part on the trigger signal;
• performing, at an operational circuit that is electrically connected to the second signal generation circuit, an operation based at least in part on the reset enable signal;
• and
• generating, at the operational circuit, a module-based reset signal based at least in part on an operation result, wherein the module-based reset signal is used to reset the exceptional timing sequence device in the functional module.