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US 11,693,448 B2Granted
Timestamp alignment across multiple computing nodes
AssigneeIntel Corporation
InventorsMark Bordogna, Jonathan A. Robinson
Life of this patent
Estimating the term…
Abstract
Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.
Claims25
A method comprising:
- a first central processing unit (CPU) node providing first and second time stamp counter (TSC) values to a separate device, wherein providing the first TSC value to the separate device causes the separate device to provide a first TSC value-primary timer value pair to the first CPU node and providing the second TSC value to the separate device causes the separate device to provide a second TSC value-primary timer value pair to the first CPU node;
- the first CPU node determining a first offset of the TSC for the first CPU node relative to the primary timer based on the first and second TSC value-primary timer value pairs received from the separate device;
- a second CPU node providing first and second TSC values to the separate device, wherein providing the first TSC value to the separate device causes the separate device to provide a first TSC value-primary timer value pair to the second CPU node and providing the second TSC value to the separate device causes the separate device to provide a second TSC value-primary timer value pair to the second CPU node;
- the second CPU node determining a second offset of the TSC for the second CPU node relative to the primary timer;
- the first CPU node adjusting the TSC for the first CPU node based on the first offset;
- and
- the second CPU node adjusting the TSC for the second CPU node based on the second offset.
4 more elements
An apparatus comprising:
- a first central processing unit (CPU) node comprising a first time stamp counter (TSC) source;
- a second CPU node comprising a second TSC source;
- an interface to an accelerator device, wherein
- by a copy of a first value of the first TSC source to the interface, the first CPU node is to initiate and cause the interface to transfer a primary time stamp value recorded for the first value of the first TSC source from the accelerator device to the first CPU node,
- by a copy of a second value of the first TSC source to the interface, the first CPU node is to initiate and cause the interface to transfer a second primary time stamp value recorded for the second value of the first TSC source from the accelerator device to the first CPU node,
- by a copy of a first value of the second TSC source to the interface, the second CPU node is to initiate and cause the interface to transfer a primary time stamp value recorded for the first value of the second TSC source from the accelerator device to the second CPU node, and
- by a copy of a second value of the second TSC source to the interface, the second CPU node is to initiate and cause the interface to transfer a second primary time stamp value recorded for the second value of the second TSC source from the accelerator device to the second CPU node.
4 more elements
A network interface comprising:
- a network interface device comprising:
- a timer source to provide a network-based timer value, wherein the timer source is based on signals received from a network;
- a precision time measurement (PTM) device to receive at least two timer values from a first central processing unit (CPU) node;
- and
- a second PTM device to receive a timer value from a second CPU node, wherein:
- receipt of a first timer value of the at least two timer values from the first CPU node is to cause:
- the PTM device to store a first network-based timer value from the timer source associated with receipt of the first timer value of the at least two timer values from the first CPU node from the first CPU node and provide a pair of the first network-based timer value from the timer source associated with the first timer value of the at least two timer values from the first CPU node to the first CPU node,
- receipt of a second timer value of the at least two timer values from the first CPU node is to cause:
- the PTM device to store a second network-based timer value from the timer source associated with receipt of the second timer value of the at least two timer values from the first CPU node from the first CPU node and provide a pair of the second network-based timer value from the timer source associated with the second timer value of the at least two timer values from the first CPU node to the first CPU node, and
- receipt of the timer value from the second CPU node is to cause:
- the second PTM device to store a network-based timer value from the timer source associated with receipt of the timer value from the second CPU node and provide a pair of the network-based timer value from the timer source associated with the timer value from the second CPU node to the second CPU node.
8 more elements
An apparatus comprising:
- a network interface device comprising:
- a first interface to a first central processing unit (CPU);
- a second interface to a second CPU;
- and
- circuitry to receive a time stamp from the first CPU by the first interface and to receive a time stamp from the second CPU by the second interface, wherein:
- receipt of the time stamp from the first CPU by the first interface is to cause the circuitry to provide, to the first CPU, a time stamp value based on a clock signal from a clock source corresponding to the received time stamp from the first CPU,
- receipt of the time stamp from the second CPU by the second interface is to cause the circuitry to provide, to the second CPU, a time stamp value based on the clock signal from the clock source corresponding to the received time stamp from the second CPU, and
- the first CPU is to adjust a time stamp counter value based, at least in part, on the time stamp value based on the clock signal corresponding to the received time stamp from the first CPU.
5 more elements
Dependencies are inferred from the claim text.