Electrostatic protection circuit of display panel, method, display panel, and display device

An electrostatic protection method of a display panel, wherein the display panel comprises an array substrate, at least a chip on film (COF) substrate connected to the array substrate, and a plurality of line electrodes parallel to each other and disposed on the array substrate, wherein the method comprises:

• disposing a first testing line, a second testing line, and a third testing line respectively connected to a data line configured to test a R signal, a G signal, and a B signal of the display panel, during a process of testing an image quality of the display panel;
• choosing three adjacent line electrodes from the plurality of line electrodes parallel to each other, and connecting the three adjacent line electrodes sequentially to the first testing line, the second testing line, and the third testing line respectively, until all of the plurality of line electrodes parallel to each other are connected to the first testing line, the second testing line, and the third testing line respectively;
• electrically isolating the first testing line, the second testing line, and the third testing line from the plurality of line electrodes parallel to each other to obtain three remaining testing lines, after the process of testing the image quality of the display panel by the first testing line, the second testing line, and the third testing line;
• connecting the three remaining testing lines to a grounding line of at least the COF substrate by an electrostatic protection line;
• wherein the display panel comprises a plurality of COF substrates sequentially connected to the array substrate, and a gate on array (GOA) signal of the display panel is imported into the display panel only through a first COF substrate and a last COF substrate, wherein the electrostatic protection method further comprises:
• connecting a plurality of first soldering pins of a remaining COF substrate, except first soldering pins of the first COF substrate and of the last COF substrate, to the grounding line of the COF substrate, wherein the plurality of first soldering pins of the remaining COF substrate are disposed on a same position of a plurality of soldering pins of the first COF substrate and the last COF substrate configured to input the GOA signal.