Image test system, test assembly and image capture card

A test assembly arranged in an image test system having an image capture card, comprising:

• a first transmission interface for obtaining a test signal from a test object;
• a test signal clock generation circuit for obtaining a test signal clock from the test signal, and transmitting the test signal clock to the image capture card;
• an interface conversion circuit for converting signal transmission form of the test signal to form a converted test signal;
• and
• a second transmission interface for transmitting the converted test signal to the image capture card,
• wherein the test signal comprises a first sub-signal, a second sub-signal and a third sub-signal, and the test signal clock generation circuit comprises a first input terminal, a first clock obtaining module, a second input terminal, a second clock obtaining module, a third input terminal, a third clock obtaining module and a circuit output terminal, and wherein the first input terminal is provided for obtaining the first sub-signal, the first clock obtaining module is provided for obtaining a first sub-signal clock from the first sub-signal and transmitting the first sub-signal clock to the circuit output terminal, the second input terminal is provided for obtaining the second sub-signal, the second clock obtaining module is provided for obtaining a second sub-signal clock from the second sub-signal and transmitting the second sub-signal clock to the circuit output terminal, the third input terminal is provided for obtaining the third sub-signal, the third clock obtaining module is provided for obtaining a third sub-signal clock from the third sub-signal and transmitting the third sub-signal clock to the circuit output terminal, and the circuit output terminal is provided for combining the first sub-signal clock, the second sub-signal clock and the third sub-signal to form the test signal clock.

An image capture card arranged in an image test system having a test assembly configured to obtain a test signal from a test object and provided with an interface conversion circuit for converting signal transmission form of the test signal to form a converted test signal, comprising:

• a test signal clock generation circuit for obtaining the converted test signal from the test assembly, and obtaining a test signal clock from the test signal;
• and
• a logic processing unit for obtaining an image data from the test signal according to the test signal clock,
• wherein the test signal comprises a first sub-signal, a second sub-signal and a third sub-signal, and the test signal clock generation circuit comprises a first input terminal, a first clock obtaining module, a second input terminal, a second clock obtaining module, a third input terminal, a third clock obtaining module and a circuit output terminal, and wherein the first input terminal is provided for obtaining the first sub-signal, the first clock obtaining module is provided for obtaining a first sub-signal clock from the first sub-signal and transmitting the first sub-signal clock to the circuit output terminal, the second input terminal is provided for obtaining the second sub-signal, the second clock obtaining module is provided for obtaining a second sub-signal clock from the second sub-signal and transmitting the second sub-signal clock to the circuit output terminal, the third input terminal is provided for obtaining the third sub-signal, the third clock obtaining module is provided for obtaining a third sub-signal clock from the third sub-signal and transmitting the third sub-signal clock to the circuit output terminal, and the circuit output terminal is provided for combining the first sub-signal clock, the second sub-signal clock and the third sub-signal to form the test signal clock.