Display panel for reducing coupling capacitance between gate of driving transistor and data line and display device

A display panel, comprising:

• a plurality of pixel circuits arranged in a matrix;
• and
• a blocking unit,
• wherein each of the plurality of pixel circuits comprises:
• a driving transistor having a gate electrode and a first electrode;
• a first switch transistor having a gate electrode electrically connected to a first scanning signal line, a first electrode electrically connected to a reference voltage signal line, and a second electrode electrically connected to the gate electrode of the driving transistor;
• a second switch transistor, having a gate electrode electrically connected to a second scanning signal line, a first electrode electrically connected to a data line, and a second electrode electrically connected to the first electrode of the driving transistor;
• and
• a third switch transistor having a gate electrode electrically connected to a light-emitting control signal line, a first electrode electrically connected to a power supply voltage signal line, and a second electrode electrically connected to the first electrode of the driving transistor, and
• wherein the blocking unit is configured to directly receive a fixed potential signal, and at least a partial area of the blocking unit is located between a first semiconductor connection portion and a second semiconductor connection portion that is mechanically disconnected from the blocking unit, the first semiconductor connection portion is a semiconductor electrically connected between the second electrode of the first switch transistor and the gate electrode of the driving transistor, and the second semiconductor connection portion is a semiconductor electrically connected between the first electrode of the second switch transistor and the data line;
• wherein the first semiconductor connection portion and the second semiconductor connection portion are arranged along a straight line parallel to the second scanning signal line, and at least a part of the blocking unit is located between the first semiconductor connection portion and the second semiconductor connection portion along the straight line;
• wherein the blocking unit comprises a first blocking unit disposed between the first semiconductor connection portion and the second semiconductor connection portion of a same pixel circuit;
• wherein the first blocking unit, the first semiconductor connection portion and the second semiconductor connection portion each have an upper edge and a lower edge that extend in a first direction, the upper edge being close to the second scanning signal line and the lower edge being close to the reference voltage signal line;
• wherein an extension line of the upper edge of the first blocking unit is located between the upper edge of the first semiconductor connection portion and the second scanning signal line, and an extension line of the lower edge of the first blocking unit is located between the lower edge of the second semiconductor connection portion and the reference voltage signal line;
• and
• wherein the extension line of the upper edge of the first blocking unit is located between a widening portion of the second semiconductor connection portion and the second scanning signal line, wherein the widening portion has a width in a row direction and the width is greater than a width of the gate electrode of the second switch transistor in the row direction.

A display panel, comprising:

• a plurality of pixel circuits arranged in a matrix;
• and
• a blocking unit,
• wherein each of the plurality of pixel circuits comprises:
• a driving transistor having a gate electrode and a first electrode;
• a first switch transistor having a gate electrode electrically connected to a first scanning signal line, a first electrode electrically connected to a reference voltage signal line, and a second electrode electrically connected to the gate electrode of the driving transistor;
• a second switch transistor, having a gate electrode electrically connected to a second scanning signal line, a first electrode electrically connected to a data line, and a second electrode electrically connected to the first electrode of the driving transistor;
• and
• a third switch transistor having a gate electrode electrically connected to a light-emitting control signal line, a first electrode electrically connected to a power supply voltage signal line, and a second electrode electrically connected to the first electrode of the driving transistor,
• wherein the blocking unit is configured to directly receive a fixed potential signal, and at least a partial area of the blocking unit is located between a first semiconductor connection portion and a second semiconductor connection portion that is mechanically disconnected from the blocking unit, the first semiconductor connection portion is a semiconductor electrically connected between the second electrode of the first switch transistor and the gate electrode of the driving transistor, and the second semiconductor connection portion is a semiconductor electrically connected between the first electrode of the second switch transistor and the data line;
• wherein the first semiconductor connection portion and the second semiconductor connection portion are arranged along a straight line parallel to the second scanning signal line, and at least a part of the blocking unit is located between the first semiconductor connection portion and the second semiconductor connection portion along the straight line;
• and
• wherein the blocking unit does not overlap with the second semiconductor connection portion.