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US 11,690,233 B2Granted
Three-dimensional memory device having parallel trench type capacitor
AssigneeSK hynix Inc.
InventorWon Seok Kim
Life of this patent
Estimating the term…
Abstract
A 3D memory device may include a logic device layer on a substrate and a memory device layer stacked on the logic device layer. The logic device layer may include logic devices disposed on the substrate. The memory device layer may include a word line stack disposed in an extension area, staircase patterns disposed in the word line stack, a dielectric layer stack in a peripheral area, and capacitors inlayed in the dielectric layer stack.
Claims19
A three-dimensional memory device comprising:
- a logic device layer on a substrate;
- and
- a memory device layer stacked on the logic device layer,
- wherein the logic device layer includes logic devices disposed on the substrate,
- wherein the memory device layer includes:
- a word line stack disposed in an extension area;
- staircase patterns disposed in the word line stack;
- a dielectric layer stack in a peripheral area;
- and
- capacitors inlayed in the dielectric layer,
- wherein the capacitors include a first capacitor having a first capacitor electrodes and a second capacitor having a second capacitor electrodes,
- wherein:
- the first capacitor electrodes have a first height,
- the second capacitor electrodes have a second height, and
- the first height is less than the second height.
12 more elements
A three-dimensional memory device comprising:
- a substrate having an extension area and a peripheral area;
- a word line stack disposed in the extension area, the word line stack including first insulating layers and word lines alternately stacked;
- a plurality of staircase patterns disposed in the word line stack;
- a dielectric layer stack disposed in the peripheral area;
- and
- capacitor electrodes disposed in the dielectric layer in parallel with each other,
- wherein the capacitor electrodes include left capacitor electrodes and right capacitor electrodes that are inlayed in the dielectric layer and that have a wall-like shape.
4 more elements
A three-dimensional memory device comprising:
- a logic device layer on a substrate;
- and
- a memory device layer stacked on the logic device layer,
- wherein the logic device layer includes logic devices disposed on the substrate,
- wherein the memory device layer includes:
- a word line stack disposed in an extension area;
- a plurality of staircase patterns disposed in the word line stack;
- a dielectric layer stack disposed in a peripheral area;
- and
- a plurality of capacitors disposed in the dielectric layer,
- wherein the word line stack includes first insulating layers and word lines alternately stacked,
- wherein the dielectric layer includes the first insulating layers and second insulating layers alternately stacked, and
- wherein the plurality of capacitors include first capacitor electrodes having a first height, second capacitor electrodes having a second height, and third capacitor electrodes having a third height.
10 more elements
Dependencies are inferred from the claim text.