High density memory devices with low cell leakage and methods for forming the same

At least two adjacent resistive random access memory cells:

• wherein:
• each of the at least two adjacent resistive random access memory cells comprises a first rail structure that extends along a first horizontal direction and is laterally spaced apart from an adjacent first rail structure along a second horizontal direction, wherein each of the first rail structures comprises a bottom electrode;
• each of the at least two memory cells comprises a second rail structure that laterally extends along the second horizontal direction and is laterally spaced apart from an adjacent second rail structure along the first horizontal direction, wherein each of the second rail structures comprises a top electrode;
• a continuous dielectric memory layer formed between the first rail structures and the second rail structures, wherein the continuous dielectric memory layer comprises a resistive switching material and spans a full length and width of the first rail structures and the second rail structures, and
• at least one of the bottom electrode and the top electrode is electrically connected to a respective metal interconnect structure formed above the at least one of the bottom electrode and the top electrode.

A method of forming a memory device, comprising:

• forming a first array of rail structures over a substrate that extend along a first horizontal direction;
• forming a continuous dielectric memory layer located over the first array of rail structures;
• forming a second array of rail structures over the continuous dielectric memory layer, wherein the second array of rail structures laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction,
• wherein:
• the continuous dielectric memory layer comprises a plate shape that spans a full length and width of the first array of rail structures and a second array of rail structures,
• each of the rail structures in the first array of rails structures comprises a bottom electrode, and
• each of the rail structures in the second array of rails structures comprises a top electrode;
• and
• directly connecting at least one of the bottom electrode and the top electrode to a respective metal interconnect structure formed above the at least one of the bottom electrode and the top electrode.

A memory device, comprising:

• bottom electrode rails that extend along a first horizontal direction and are laterally spaced apart along a second horizontal direction;
• top electrode rails that laterally extend along the second horizontal direction and are laterally spaced apart along the first horizontal direction;
• a continuous dielectric memory layer located between the bottom electrode rails and the top electrode rails, wherein the continuous dielectric memory layer spans a full length and a full width of the bottom electrode rails and spans a full length and a full width of the top electrode rails;
• and
• bit line contact structures vertically extending through the continuous dielectric memory layer and contacting a top surface of a respective one of the bottom electrode rails.