Charge pump circuit capable of generating voltages in erasing operation, program operation and read operation

A charge pump circuit for generating a first voltage in an erasing operation, a second voltage in a program operation and a third voltage in a read operation, the charge pump circuit comprising:

• a power switch comprising a first terminal configured to receive an input voltage, a second terminal and a control terminal configured to receive an enabling signal;
• a first pull-low circuit comprising a first terminal configured to receive a pull-low signal, and a second terminal;
• a second pull-low circuit comprising a first terminal configured to receive the pull-low signal, and a second terminal;
• an output pull-low circuit comprising a first terminal configured to receive the pull-low signal, and a second terminal;
• a first charge pump stage comprising:
• a first boost capacitor comprising a first terminal configured to receive a fourth phase signal, and a second terminal;
• a first transfer transistor comprising a first terminal coupled to the second terminal of the power switch, a second terminal, and a control terminal coupled to the second terminal of the first boost capacitor and the second terminal of the first pull-low circuit;
• a first gate-control transistor comprising a first terminal coupled to the control terminal of the first transfer transistor, a second terminal coupled to the second terminal of the first transfer transistor, and a control terminal coupled to the second terminal of the power switch;
• and
• a first storage capacitor comprising a first terminal configured to receive a third phase signal, and a second terminal coupled to the second terminal of the first transfer transistor;
• a second charge pump stage comprising:
• a second boost capacitor comprising a first terminal configured to receive a first phase signal, and a second terminal;
• a second transfer transistor comprising a first terminal coupled to the second terminal of the first storage capacitor, a second terminal, and a control terminal coupled to the second terminal of the second boost capacitor and the second terminal of the second pull-low circuit;
• a second gate-control transistor comprising a first terminal coupled to the control terminal of the second transfer transistor, a second terminal coupled to the second terminal of the second transfer transistor, and a control terminal coupled to the second terminal of the first storage capacitor;
• and
• a second storage capacitor comprising a first terminal configured to receive a second phase signal, and a second terminal coupled to the second terminal of the second transfer transistor;
• and
• an output charge pump stage comprising:
• an output boost capacitor comprising a first terminal configured to receive the third phase signal, and a second terminal;
• an output transfer transistor comprising a first terminal coupled to the second terminal of the second storage capacitor, a second terminal configured to output the first voltage, the second voltage or the third voltage, and a control terminal coupled to the second terminal of the output boost capacitor and the second terminal of the output pull-low circuit;
• and
• an output gate-control transistor comprising a first terminal coupled to the control terminal of the output transfer transistor, a second terminal coupled to the second terminal of the output transfer transistor, and a control terminal coupled to the second terminal of the first storage capacitor.