Semiconductor devices having a decreasing height gate structure

A semiconductor device comprising:

• first, second and third gate structures spaced apart from each other on a substrate;
• first and second spacer structures on first and second sidewalls, respectively, opposite to each other of each of the first, second, and third gate structures;
• and
• first, second, third, and fourth source/drain layers at upper portions of the substrate between the first and second gate structures, between the second and third gate structures, at one side of the first gate structure, and at one side of the third gate structure, respectively,
• wherein the first and second gate structures are spaced apart from each other by a first distance, and the second and third gate structures are spaced apart from each other by a second distance greater than the first distance,
• wherein an uppermost surface of the first spacer structure on the first sidewall of the second gate structure facing the first gate structure is lower than an uppermost surface of the second spacer structure on the second sidewall of the second gate structure with reference to an upper surface of the substrate being a base level, and
• wherein an uppermost surface of the first spacer structure on the first sidewall of the first gate structure facing the second gate structure is lower than an uppermost surface of the second spacer structure on the second sidewall of the first gate structure with reference to the upper surface of the substrate being the base level.

A semiconductor device comprising:

• first and second active patterns on a cell region and a peripheral circuit region, respectively, of a substrate, the peripheral circuit region surrounding the cell region in a plan view of the semiconductor device;
• a first gate structure buried at an upper portion of the first active pattern;
• a bit line structure physically contacting a central upper surface of the first active pattern;
• a contact plug structure physically contacting each of opposite edge upper surfaces of the first active pattern;
• a capacitor on the contact plug structure;
• a second gate structure on the second active pattern;
• first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the second gate structure;
• and
• first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the second gate structure,
• wherein an upper surface of the second gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall,
• wherein the first spacer structure includes a first spacer, a first etch stop pattern, and a third spacer sequentially stacked from the first sidewall of the gate structure in a direction substantially parallel to the upper surface of the substrate,
• wherein the second spacer structure includes a second spacer, a second etch stop pattern, and a fourth spacer sequentially stacked from the second sidewall of the gate structure in the direction substantially parallel to the upper surface of the substrate,
• wherein each of the first and second spacers includes silicon oxide or a metal oxide, and a cross-section of each of the first and second etch stop patterns has an “L” shape, and
• wherein an uppermost surface of the second etch stop pattern is substantially coplanar with an uppermost surface of the gate structure.