US 11,690,212 B2 · Memory architecture at back-end-of-line

Abstract

Embodiments herein describe techniques for a semiconductor device including a substrate. A first set of memory cells and a first selector are formed within a first group of metal layers and inter-level dielectric (ILD) layers above the substrate. A second set of memory cells and a second selector are formed within a second group of metal layers and ILD layers above the first group of metal layers and ILD layers. The first selector is coupled to the first set of memory cells to select one or more memory cells of the first set of memory cells based on a first control signal. In addition, the second selector is coupled to the second set of memory cells to select one or more memory cells of the second set of memory cells based on a second control signal. Other embodiments may be described and/or claimed.

Claims24

Dependent claims

A semiconductor device, comprising:

a substrate;
a first set of memory cells formed within a first group of metal layers and inter-level dielectric (ILD) layers above the substrate;
a first selector formed within the first group of metal layers and ILD layers and coupled to the first set of memory cells to select one or more memory cells of the first set of memory cells based on a first control signal;
a second set of memory cells formed within a second group of metal layers and ILD layers above the first group of metal layers and ILD layers;
and
a second selector within the second group of metal layers and ILD layers and coupled to the second set of memory cells to select one or more memory cells of the second set of memory cells based on a second control signal, wherein the first set of memory cells and the second set of memory cells are coupled to a same bitline through the first selector and the second selector.

3 more elements

A computing device, comprising:

a circuit board;
and
a memory device coupled to the circuit board, wherein the memory device includes:
a first set of memory cells formed within a first group of metal layers and inter-level dielectric (ILD) layers above the substrate;
a first selector formed within the first group of metal layers and ILD layers and coupled to the first set of memory cells to select one or more memory cells of the first set of memory cells based on a first control signal;
a second set of memory cells formed within a second group of metal layers and ILD layers above the first group of metal layers and ILD layers;
and
a second selector within the second group of metal layers and ILD layers and coupled to the second set of memory cells to select one or more memory cells of the second set of memory cells based on a second control signal, wherein the first set of memory cells and the second set of memory cells are coupled to a same bitline through the first selector and the second selector.

5 more elements

Dependencies are inferred from the claim text.

Memory architecture at back-end-of-line

Life of this patent

Memory architecture at back-end-of-line

Life of this patent

Abstract

Claims24