Three-dimensional dynamic random-access memory array

A memory cell formed within a substrate comprising a dielectric device level and at least one electrically conductive device level vertically adjacent the dielectric device level, the memory cell comprising:

• a transistor comprising,
• a semiconductor ring formed within a dielectric device level in electrical contact with a first conductive pillar extending vertically through the dielectric and conductive device levels, the first conductive pillar connected to a source node, and
• at least one electrically conductive ring forming at least one respective transistor gate within the at least one electrically conductive device level surrounding the first conductive pillar, the transistor gate being electrically insulated from the first conductive pillar and the semiconductor ring and being connected to a gate voltage;
• and
• a capacitor comprising
• a conductive ring forming a capacitor node plate within the dielectric device level at least partially surrounding and in electrical contact with the semiconductor ring, the capacitor node plate being electrically insulated from a second conductive pillar extending through the dielectric and conductive device levels, the second conductive pillar connected to a ground node, and
• a ground plate formed by portions of the conductive device level electrically connected to the second conductive pillar and horizontally overlapping with the capacitor node plate.

A method of forming a DRAM array, comprising:

• forming multiple device-tiers over a substrate, the multiple device tiers vertically separated from one another by dielectric separation levels, each of the device tiers comprising a dielectric device level and at least one conductive device level;
• forming electrically conductive data-line pillars vertically extending through at least a portion of the device tiers and the dielectric separation levels, the data-line pillars spaced along multiple first rows;
• forming electrically conductive ground pillars vertically extending through at least a portion of the device tiers and the dielectric separation levels, the ground pillars spaced along multiple second rows, the first and second rows both extending in a first horizontal direction and alternating with one another in a second horizontal direction, the first rows do not include ground pillars and the second rows do not include data-line pillars;
• and
• forming memory cells within the device tiers, the memory cells at least partially surrounding a respective one of the conductive data-line pillars, and comprising a transistor and a capacitor coupled between a data-line pillar and one or more of the ground pillars, the data-line pillars corresponding to data lines to supply a source voltage to the transistors, and the ground pillars to be coupled to a reference voltage,
• wherein the memory cells comprise rows of memory cells extending in the first horizontal direction, and wherein transistors of the memory cells within each row and within a conductive device level share a common access line.