Fin-based well straps for improving memory macro performance

An integrated circuit device comprising:

• an n-type well disposed in a substrate, the n-type well being continuous and doped with an n-type dopant;
• a first transistor disposed over the n-type well, wherein the first transistor has a first fin structure and a first gate structure disposed over the first fin structure, such that the first gate structure interposes first source/drain (S/D) features of the first transistor;
• a first well strap disposed over the n-type well, wherein the first well strap has a second fin structure electrically connected to the n-type well and a second gate structure disposed over the second fin structure, such that the second gate structure interposes second S/D features of the first well strap;
• a p-type well disposed in the substrate and abut the n-type well, the p-type well being continuous and doped with a p-type dopant;
• a second transistor disposed over the p-type well, wherein the second transistor has a third fin structure and a third gate structure disposed over the third fin structure, such that the third gate structure interposes third S/D features of the second transistor;
• and
• a second well strap disposed over the p-type well, wherein the second well strap has a fourth fin structure electrically connected to the p-type well and a fourth gate structure disposed over the fourth fin structure, such that the fourth gate structure interposes fourth S/D features of the second well strap,
• wherein a bottom surface of the second S/D features is below a bottom surface of the first S/D features, wherein each of the second and fourth fin structures is wider than the first fin structure, and wherein a center line of the first fin structure is offset and parallel to a center line of the second fin structure.

A memory circuit comprising:

• a first FinFET disposed over a doped region of a first type dopant, wherein the first FinFET includes a first fin structure and first source/drain (S/D) features disposed on the first fin structure, the first S/D features having a first volume;
• a fin-based well strap disposed over the doped region of the first type dopant, wherein the fin-based well strap includes a second fin structure and second S/D features disposed on the second fin structure, the second S/D features having a second volume that is larger than the first volume, wherein the fin-based well strap connects the doped region to a voltage node of the memory circuit, wherein a bottom surface of the second S/D features is below a bottom surface of the first S/D features;
• and
• a second FinFET disposed over the doped region of the first type dopant, wherein the second FinFET includes a third fin structure and third S/D features disposed on the third fin structure, the doped region of the first type dopant is continuous, and a center line of the second fin structure is located between a center line of the first fin structure and a center line of the third fin structure.