Multilayer printed wiring board and method of manufacturing the same
AssigneeToppan Printing Co., Ltd.
InventorHiroshi Matsumoto
Life of this patent
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Abstract
A multilayer printed wiring board and a method of manufacturing the same are provided. A multilayer printed wiring board of the present embodiment includes: a core base material formed by laminating a first wiring layer and a first insulating layer in this order on an insulating substrate; and a built-up layer formed by laminating a second wiring layer and a second insulating layer in this order on the core base material. A primer layer is formed between the second wiring layer and the first insulating layer, the second wiring layer has a lower surface at least part of which is in contact with the primer layer, and the second wiring layer has an upper surface and a side surface on both of which a tin-plated layer and a silane coupling layer are formed in this order.
Claims9
A method of manufacturing a multilayer printed wiring board including a plurality of layers formed on a laminate that is a lamination of an insulating substrate and a first wiring layer formed on the insulating substrate, wherein the method comprises:
- forming a first insulating layer on the laminate so as to cover the first wiring layer;
- forming a primer layer on the first insulating layer without forming a copper layer on the primer layer, the primer layer increasing adhesion between the first insulating layer and a copper electroless-plated layer;
- forming via holes penetrating the primer layer, and the first insulating layer to expose a surface of the first wiring layer;
- performing desmear treatment for removing smears generated in the via holes;
- forming the copper electroless-played layer on the surface of the primer layer and bottom surfaces and sidewall surfaces of the via holes;
- forming a resist pattern on a surface of the copper electroless-plated layer in regions where a second wiring layer is not to be formed, the resist pattern serving as a plating mask;
- forming the copper electroplated layer on a surface of the copper electroless-plated layer in regions where the resist pattern has not been formed;
- peeling the resist pattern;
- removing the copper electroless-plated layer in regions empty of the resist pattern to form a second wiring layer and expose the surface of the primer layer, the second wiring layer including the copper electroless-plated layer and the copper electroplated layer;
- forming a tin-plated layer on a surface of the second wiring layer and then forming a silane coupling layer on the surface of the tin-plated layer;
- and
- forming a second insulating layer so as to cover the primer layer and the second wiring layer where the tin-plated layer and the silane coupling layer have been formed.
A method of manufacturing a multilayer printed wiring board including a plurality of layers formed on a laminate that is a lamination of an insulating substrate and a first wiring layer formed on the insulating substrate, wherein the method comprises:
- forming a first insulating layer on the laminate so as to cover the first wiring layer;
- forming a primer layer on the first insulating layer without forming a copper layer on the primer layer, the primer layer increasing adhesion between the first insulating layer and a copper electroless-plated layer;
- forming via holes penetrating the primer layer, and the first insulating layer to expose a surface of the first wiring layer;
- performing desmear treatment for removing smears generated in the via holes;
- forming the copper electroless-plated layer on the surface of the primer layer and bottom surfaces and sidewall surfaces of the via holes;
- forming a resist pattern on a surface of the copper electroless-plated layer in regions where a second wiring layer is not to be formed, the resist pattern serving as a plating mask;
- forming a copper electroplated layer on the surface of the copper electroless-plated layer in regions where the resist pattern has not formed;
- peeling the resist pattern;
- removing the copper electroless-plated layer in regions empty of the resist pattern to form a second wiring layer and expose the surface of the primer layer, the second wiring layer including the copper electroless-plated layer and the copper electroplated layer;
- forming a silane coupling layer on the surface of the second wiring layer;
- and
- forming a second insulating layer so as to cover the primer layer and the second wiring layer where the silane coupling layer has been formed.
Dependencies are inferred from the claim text.