US 11,689,850 B2Granted

Sound source separation device, semiconductor device, and electronic device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsTakeya Hirose, Takayuki Ikeda

Life of this patent

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Abstract

Provided is a semiconductor device that does not require an A/D converter circuit and is capable of performing sound source separation without converting an analog signal. The semiconductor device includes a plurality of microphones, a plurality of delay circuits, and a signal processing circuit. The plurality of microphones are electrically connected to the respective delay circuits, and output signals of the plurality of delay circuits are input to the signal processing circuit. The delay circuit includes a plurality of signal retention circuits capable of retaining an analog potential, and has functions of retaining an electric signal output from the microphone as a discrete analog signal in the signal retention circuits and outputting the signal at a time different from the time when the microphone outputs the signal. The signal processing circuit has a function of adding the output signals of the plurality of delay circuits.

Claims12

Dependent claims

A semiconductor device comprising:

a first selection circuit comprising a first transistor;
a first signal retention circuit comprising a second transistor;
a second signal retention circuit;
and
a second selection circuit comprising a third transistor,
wherein an analog signal is input to the semiconductor device,
wherein the first selection circuit is configured to select one of the first signal retention circuit and the second signal retention circuit,
wherein the first signal retention circuit is configured to sample the analog signal at different times and to retain a first analog potential depended on the analog signal,
wherein the second signal retention circuit is configured to sample the analog signal at different times and to retain a second analog potential depended on the analog signal,
wherein the second selection circuit is configured to output one of the first analog potential and the second analog potential,
wherein the one of the first analog potential and the second analog potential which is output is a signal delayed from the analog signal,
wherein one of source and drain of the first transistor is electrically connected to a gate of the second transistor, and
wherein one of source and drain of the second transistor is electrically connected to one of source and drain of the third transistor.

10 more elements

A semiconductor device comprising:

a first microphone outputting a first sound source signal;
a second microphone outputting a second sound source signal;
a first delay circuit being input the first sound source signal from the first microphone, and the first delay circuit configured to generate a first signal delayed from the first sound source signal;
a second delay circuit being input the second sound source signal from the second microphone, and the second delay circuit configured to generate a second signal delayed from the second sound source signal;
and
a signal processing circuit configured to add the first signal and the second signal,
wherein the first delay circuit and the second delay circuit each comprises:
a first selection circuit comprising a first transistor;
a first signal retention circuit comprising a second transistor;
a second signal retention circuit;
and
a second selection circuit comprising a third transistor,
wherein one of source and drain of the first transistor is electrically connected to a gate of the second transistor, and
wherein one of source and drain of the second transistor is electrically connected to one of source and drain of the third transistor.

11 more elements

A semiconductor device comprising:

a first microphone outputting a first sound source signal;
a second microphone outputting a second sound source signal;
a third microphone outputting a third sound source signal;
a first delay circuit being input the first sound source signal from the first microphone, and the first delay circuit configured to generate a first signal delayed from the first sound source signal;
a second delay circuit being input the second sound source signal from the second microphone, and the second delay circuit configured to generate a second signal delayed from the second sound source signal;
and
a signal processing circuit configured to add the first signal, the second signal, and the third sound source signal,
wherein the first delay circuit and the second delay circuit each comprises:
a first selection circuit comprising a first transistor;
a first signal retention circuit comprising a second transistor;
a second signal retention circuit;
and
a second selection circuit comprising a third transistor,
wherein one of source and drain of the first transistor is electrically connected to a gate of the second transistor, and
wherein one of source and drain of the second transistor is electrically connected to one of source and drain of the third transistor.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/282,106Filed 2 Oct 2019
Priority: JP 2018-19287711 Oct 2018
Published: US 2021/0400382 A123 Dec 2021
Granted: 27 Jun 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H04R 3/005
Circuits for transducers: for combining the signals of two or more microphones
H03M 1/12
Analogue/digital conversion; Digital/analogue conversion: analogue/digital converters
H04R 1/406
By combining a number of identical transducers: microphones
H10B 12/00
Dynamic random access memory [dram] devices