Parallel filter structure, oscilloscope and method of processing a signal

A method of processing a signal, wherein the method comprises the steps of:

• receiving a time and value discrete input signal via a signal input;
• filtering the time and value discrete input signal by a feed forward equalizer circuit of a parallel filter structure;
• and
• filtering the time and value discrete input signal by a decision feedback equalizer circuit of the parallel filter structure, which together with the feed forward equalizer circuit forms a parallel circuit of the parallel filter structure,
• wherein the parallel filter structure comprises a first output interface associated with the feed forward equalizer circuit such that an output signal of the feed forward equalizer circuit is fed to the first output interface, wherein the parallel filter structure is connectable with a separately formed chip on which a trigger circuit is provided via the first output interface,
• wherein the parallel filter structure comprises a second output interface associated with the decision feedback equalizer circuit such that an output signal of the decision feedback equalizer circuit is fed to the second output interface, wherein the parallel filter structure is connectable with a separately formed chip on which an eye diagram circuit is provide via the second output interface, and wherein the first output interface and the second output interface are separate output interfaces.

A parallel filter structure for processing a signal, the parallel filter structure comprising:

• a processing circuit;
• a signal input configured to receive a time and value discrete input signal;
• a feed forward equalizer circuit directly connected via a first line with the signal input for receiving the time and value discrete input signal;
• and
• a decision feedback equalizer circuit directly connected via a second line with the signal input for receiving the time and value discrete input signal,
• wherein the feed forward equalizer circuit and the decision feedback equalizer circuit together form a parallel circuit, wherein the feed forward equalizer circuit and the decision feedback equalizer circuit both are connected with the signal input such that the feed forward equalizer circuit and the decision feedback equalizer circuit both process the same time and value discrete input signal in parallel that was received via the signal input, and
• wherein the feed forward equalizer circuit and the decision feedback equalizer circuit both provide output signals in parallel that are forwarded to the processing circuit that processes the respective output signals.