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US 11,689,361 B1Granted
Distributed key expansion
AssigneeXilinx, Inc.
InventorsDevanjan Maiti, Robert Bellarmin Susai, Jayaram Pvss
Life of this patent
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Abstract
N key generation circuits are arranged in a pipeline having N stages. Each key generation circuit is configured to generate a round key as a function of a respective input key and a respective round constant. Output signal lines that carry the round key from a key generation circuit in a stage of the pipeline, except the key generation circuit in a last stage of the pipeline, are coupled to the key generation circuit in a successive stage of the pipeline to provide the respective input key.
Claims19
A circuit arrangement comprising:
- a plurality of N key generation circuits arranged in a pipeline having N stages;
- wherein each key generation circuit is configured to generate a round key as a function of a respective input key and a respective round constant;
- wherein each key generation circuit has a respective set of signal lines coupled to first and second power rails to provide the respective round constant, the first power rail has a voltage level indicative of a bit value 1, and the second power rail has a voltage level indicative of a bit value 0;
- and
- wherein output signal lines that carry the round key from the key generation circuit in a stage of the N stages of the pipeline, except the key generation circuit in a last stage of the N stages of the pipeline, are coupled to the key generation circuit in a successive stage of the pipeline to provide the respective input key.
2 more elements
A method, comprising:
- generating N round keys in parallel by N key generation circuits, respectively, wherein the N key generation circuits are arranged in a pipeline having stages 0 through N−1, and each key generation circuit generates the respective round key as a function of a respective input key and a respective round constant;
- providing the round keys generated by the key generation circuits in stages 0 through N−2 as the input keys to the key generation circuit in stages 1 through N−1, respectively;
- and
- inputting the respective round constants in parallel to the key generation circuits by respective sets of signal lines coupled to first and second power rails to provide the respective round constants, wherein the first power rail has a voltage level indicative of a bit value 1, and the second power rail has a voltage level indicative of a bit value 0.
1 more element
Dependencies are inferred from the claim text.