Hybrid serial receiver circuit
AssigneeApple Inc.
InventorsRyan D. Bartling, Jafar Savoj, Brian S. Leibowitz
Life of this patent
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Abstract
A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
Claims20
An apparatus, comprising:
- a front-end circuit configured to generate an equalized signal using at least one signal that encodes a serial data stream that includes a plurality of data symbols;
- an ADC-based receiver circuit that includes at least one analog-to-digital converter circuit, wherein the ADC-based receiver circuit is configured, based on a baud rate of the serial data stream, to generate a first plurality of recovered data symbols using the equalized signal and a plurality of first clock signals;
- a first analog receiver circuit configured, based on the baud rate of the serial data stream, to generate a second plurality of recovered data symbols using the equalized signal and a plurality of second clock signals;
- and
- a clock circuit configured to:
- generate the plurality of first clock signals using first control information determined during a generation of the first plurality of recovered data symbols;
- and
- generate the plurality of second clock signals using second control information determined during a generation of the second plurality of recovered data symbols.
A method, comprising:
- generating an equalized signal using at least one signal that encodes a serial data stream that includes a plurality of data symbols;
- activating, based on an operating condition, a particular receiver circuit of a plurality of receiver circuits, wherein the particular receiver circuit includes at least one analog-to-digital converter circuit;
- generating, by the particular receiver circuit, a first plurality of recovered data symbols using the equalized signal and a particular set of clock signals;
- and
- generating, by a clock circuit, the particular set of clock signals using particular control information determined during the generation of the first plurality of recovered data symbols.
An apparatus, comprising:
- a first device that includes a first functional circuit block, wherein the first device is configured to:
- receive, from the first functional circuit block, a serial data stream that includes a plurality of data symbols;
- generate a plurality of signals that encode the serial data stream;
- and
- transmit the plurality of signals via a communication channel;
- and
- a second device that includes a plurality of receiver circuits, wherein the second device is configured to:
- receive the plurality of signals via the communication channel;
- generate an equalized signal using the plurality of signals;
- activate, based on a baud rate of the serial data stream, a particular receiver circuit of the plurality of receiver circuits, wherein the particular receiver circuit includes at least one analog-to-digital converter circuit;
- generate, by the particular receiver circuit, a first plurality of recovered data symbols using the equalized signal and a particular set of clock signals;
- and
- generate the particular set of clock signals using particular control information determined during a generation of the first plurality of recovered data symbols.
Dependencies are inferred from the claim text.