US 11,689,316 B2Granted

Reduced power transmitter during standby mode

AssigneeTexas Instruments Incorporated

InventorsSanjay Pennam, Vamsi Krishna Kandalla, Brahmendra Reddy Yatham, Shailesh Wardhen, Jaiganesh Balakrishnan, Jawaharlal Tangudu

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Abstract

A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

Claims20

Dependent claims

A transmitter, comprising:

an analog-to-digital converter (ADC);
a mapper coupled to the ADC;
a data stream encoder layer having a data stream encoder input and a data stream encoder output, the data stream encoder input coupled to the mapper, the data stream encoder layer comprising:
a multiplexer having:
a first multiplexer input;
a second multiplexer input;
a multiplexer control input;
and
a multiplexer output, wherein the multiplexer output is coupled to the data stream encoder output;
and
a pattern generator having a pattern generator input and a bit pattern output, the bit pattern output coupled to the second multiplexer input;
and
a serializer coupled to the multiplexer output;
wherein, while at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns at the bit pattern output, the multiplexer is configured to, based on receiving a control signal at the multiplexer control input, select the second multiplexer input, and the multiplexer is configured to output the bit patterns at the multiplexer output.

11 more elements

A transmitter, comprising:

a first multiplexer having:
a first multiplexer input;
a second multiplexer input;
a first multiplexer control input;
and
a first multiplexer output;
and
a pattern generator having a pattern generator input and a bit pattern output, the bit pattern output coupled to the second multiplexer input, the pattern generator comprising:
a second multiplexer having a third multiplexer input, a fourth multiplexer input, a second multiplexer control input, and a second multiplexer output, wherein the second multiplexer output is coupled to the bit pattern output, a first storage element is coupled to the third multiplexer input and a second storage element is coupled to the fourth multiplexer input;
and
a random number generator having random number generator output coupled to the second multiplexer control input.

8 more elements

A transmitter, comprising:

a multiplexer having:
a first multiplexer input;
a second multiplexer input;
a multiplexer control input;
and
a multiplexer output;
a pattern generator having a pattern generator input and a bit pattern output, the bit pattern output coupled to the second multiplexer input;
and
an error-detecting code generator having an error-detecting output coupled to the pattern generator input, the error-detecting code generator configured to:
calculate error-detecting codes;
and
provide a current error-detecting code to the pattern generator upon transition to a standby mode;
and
wherein the pattern generator is configured to generate a first bit pattern at the bit pattern output based on the current error-detecting code.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/462,055Filed 31 Aug 2021 · continuation
Priority: IN 2019410501035 Dec 2019
Published: US 2021/0176005 A116 Dec 2021
Granted: 27 Jun 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H04L 1/0044
Realisations of complexity reduction techniques, e.g. use of look-up tables: specially adapted for power saving
H04B 1/04
Transmitters: circuits
H04L 1/0042
Arrangements at the transmitter end: encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit…
H04L 1/0047
Arrangements at the receiver end: decoding adapted to other signal detection operation

Family

Application16/936,065Parent of this continuation · filed 22 Jul 2020
US 2021/0391944 A1Pre-grant publication · published 16 Dec 2021
US 11,139,916 B2Parent of this continuation
US 2021/0176005 A1Published application
US 11,689,316 B2This patent

From the US filing history. Foreign family members aren’t listed.