Method and system for error correction in memory devices using irregular error correction code components

Non-transitory computer-readable media storing computer-readable instructions, such that when executed, causes a processing circuit to optimize irregular error correction code components corresponding to a non-volatile storage device by:

• obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter;
• generating, based on one or both of the payload size parameter and the redundancy parameter, a first number of first code component blocks each having a first number of bits associated with a first error correction capability, and a second number of code component blocks each having a second number of bits associated with a second error correction capability;
• calculating an alignment between a size associated with a total of the first number of the first code component blocks and the second number of second code component blocks and the group size parameter;
• adjusting the alignment by adjusting the first number of the first code component blocks and the second number of the second code component blocks in accordance with a code component length constraint;
• and
• generating, in accordance with an optimization metric associated with the first error correction capability and the second error correction capability, first optimized code components based on the adjusted first number of first code component blocks and second optimized code components based on the adjusted second number of second code component blocks.