Architecture for analog multiplier-accumulator with binary weighted charge transfer capacitors

A multiplier-accumulator (MAC) with Analog to Digital Converter (ADC) comprising:

• a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line;
• a first plurality of MAC unit elements (MAC UEs) coupled to the differential charge transfer bus and configured to have a digital X input and a digital W input;
• a second plurality of Bias unit elements (Bias UEs) coupled to the differential charge transfer bus and configured to have a digital E input;
• a third plurality of ADC UEs coupled to the differential charge transfer bus and configured add or subtract charge from the differential charge transfer bus;
• at least one of a MAC UE or a Bias UE has an input coupled to a NAND gate generating an output and an inverted output, each of the output and the inverted output coupled through a respective binary weighted charge transfer capacitor to the differential charge transfer bus;
• the third plurality of ADC UEs coupled to a successive approximation register (SAR) controller configured to enable or disable ADC UEs an outputting a digital result corresponding to a charge on the differential charge transfer bus.

A Multiply-accumulate (MAC) generating a digital output, the MAC comprising:

• a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line;
• a first plurality of multiplier-accumulator unit elements (MAC UEs) having a digital X input and a digital W input, the first plurality of MAC UEs coupling charge into the differential charge transfer bus as bitwise products of said input X and said input W;
• a second plurality of Bias Unit Elements (Bias UEs) coupled to the differential charge transfer bus and transferring a charge to the differential charge transfer bus according to a bias digital input;
• a third plurality of Analog to Digital Converter Unit Elements (ADC UEs) coupled to the differential charge transfer bus;
• the positive charge transfer line and negative charge transfer line coupled to a comparator, the comparator coupled to a successive approximation controller, the successive approximation controller sequentially switching increasingly smaller numbers of ADC UEs of the third plurality of ADC UEs according to the output of the comparator, each comparison generating a bit of the digital output.