Clock frequency monitoring for a phase-locked loop based design

An apparatus comprising:

• a Phase-Locked Loop (PLL) based design comprising a Digitally Controlled Oscillator (DCO) configured to generate a present frequency in response to a present operating point;
• a memory configured to store a comparison range defined by a plurality of reference operating points, wherein the DCO is configured to generate a nominal reference frequency in response to a nominal one of the plurality of reference operating points and the comparison range is further defined by a manufacturing process range, an operating voltage range and an operating temperature range;
• a capacitor bank control word configured to define a present operating point of the DCO;
• and
• a controller configured to compare at least one highest order bit of the capacitor bank control word to the comparison range performing an action in response thereto.

A method for clock frequency monitoring for a Phase-Locked Loop (PLL) design comprising:

• determining a present operating point of a digitally controlled oscillator (DCO) of the PLL based design, wherein the DCO generates a present frequency in response to the present operating point, and the present operating point is defined by a capacitor bank control word;
• comparing at least one highest order bit of the capacitor bank control word to a comparison range defined by a plurality of reference operating points, wherein the DCO generates a nominal reference frequency in response to a nominal one of the plurality of reference operating points and the comparison range is further defined by at least one environmental factor;
• and
• performing an action in response to the present operating point being outside of the comparison range.