High frequency resolution digital sinusoid generator
AssigneeSTMicroelectronics International N.V.
InventorAnkur Bal
Life of this patent
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Abstract
A delay circuit applies a one sample delay to a first digital sinusoid signal and outputs a delayed digital sinusoid signal. The first digital sinusoid signal and the delayed digital sinusoid signal are then added to each other by an adder circuit to generate an added digital sinusoid signal. A gain scaling circuit applies a scaling factor to the added digital sinusoid signal to generate a second digital sinusoid signal. Samples of the first and second digital sinusoid signals are alternately selected by a multiplexing circuit to generate a third digital sinusoid signal having twice as many samples as the first digital sinusoid signal over a same sinusoid period.
Claims38
A digital circuit, comprising:
- an input configured to receive a first digital sinusoid signal;
- a first delay circuit configured to apply a delay to the first digital sinusoid signal to generate a first delayed digital sinusoid signal;
- a first adder circuit configured to add the first digital sinusoid signal to the first delayed digital sinusoid signal to generate a first added digital sinusoid signal;
- a first gain scaling circuit configured to apply a first scaling factor to the first added digital sinusoid signal to generate a second digital sinusoid signal;
- and
- a selection circuit configured to repeatedly select samples from both the first and second digital sinusoid signals and generate an output digital sinusoid signal.
A sinusoid generator circuit, comprising:
- an input configured to receive a first digital sinusoid signal having a time domain representation corresponding to A sin(ωt);
- a processing circuit coupled to said input and configured to generate from said first digital sinusoid signal a second digital sinusoid having a time domain representation corresponding to A sin(ωt+α/2);
- wherein α is a phase shift equal to one sample of the first digital sinusoid signal;
- and
- a selection circuit having first and second inputs configured to receive the first and second digital sinusoid signals, respectively, said multiplexer circuit configured to repeatedly and sequentially select samples of the first and second digital sinusoid signals to generate a third digital sinusoid signal.
A sinusoid generator circuit, comprising:
- an input configured to receive a first digital sinusoid signal having a discrete domain representation of A sin(2πn/N), where n is an index for samples and N is a total number of samples in one sinusoid period;
- a processing circuit coupled to said input and configured to generate from said first digital sinusoid signal a second digital sinusoid having a discrete domain representation corresponding to A sin(2π(n−(½))/N);
- and
- a selection circuit having first and second inputs configured to receive the first and second digital sinusoid signals, respectively, said multiplexer circuit configured to repeatedly and sequentially select samples of the first and second digital sinusoid signals to generate a third digital sinusoid signal.
A method, comprising:
- receiving a first digital sinusoid signal;
- delaying the first digital sinusoid signal to produce a delayed digital sinusoid signal;
- adding the first digital sinusoid signal to the delayed digital sinusoid signal to generate an added digital sinusoid signal;
- apply a scaling factor to the added digital sinusoid signal to generate a second digital sinusoid signal;
- and
- repeatedly and sequentially selecting samples from the first and second digital sinusoid signals to generate a third digital sinusoid signal.
Dependencies are inferred from the claim text.