Adaptive gate drive for a power switch transistor in a switching power converter
AssigneeDialog Semiconductor GmbH
InventorsWenduo Liu, Huangxuan Gong, Vijay Kanagala, Hien Bui
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Abstract
A gate drive control circuit is provided that charges a gate voltage of a power switch transistor during a power switch transistor on-time period. During a first portion of the on-time period, the gate drive control circuit charges the gate voltage through a relatively-low resistance. During a second portion of the on-time period, the gate drive control circuit charges the gate voltage through a relatively-high resistance. Finally, during a third portion of the on-time period, the gate drive control circuit charges the gate voltage through another relatively-low resistance.
Claims18
A gate drive control circuit for a power switch transistor in a switching power converter, comprising:
- a gate drive circuit configured to charge a gate of the power switch transistor through a variable gate drive resistance;
- an adaptive drive control circuit configured to command the gate drive circuit to use a first gate drive resistance during a first portion of a power switch transistor on-time period, a second gate drive resistance during a second portion of the power switch transistor on-time period, and a third gate drive resistance during a third portion of the power switch transistor on-time period;
- and
- a gate voltage monitor configured to monitor a gate voltage of the power switch transistor, wherein the adaptive drive control circuit is further configured to end the first portion of the power switch transistor on-time period and transition to the second portion of the power switch transistor on-time period responsive to a comparison of the gate voltage of the power switch transistor to a first threshold voltage by the gate voltage monitor.
A method of adapting a gate drive resistance for a power switch transistor in a switching power converter, comprising:
- during an initial portion of a power switch transistor on-time period while a gate voltage of the power switch transistor is less than a first threshold voltage, charging a gate of the power switch transistor through a first resistance;
- initiating a timing of a maximum delay period responsive to the gate voltage of the power switch transistor being greater than the first threshold voltage;
- during a second portion of the power switch transistor on-time period prior to an expiration of the maximum delay period, charging the gate of the power switch transistor through a second resistance.
A switching power converter, comprising:
- an inductor;
- a power switch transistor connected to the inductor;
- and
- a gate drive control circuit configured to:
- charge a gate of the power switch transistor through a first resistance during a first portion of an on-time period for the power switch transistor, charge the gate of the power switch transistor through a second resistance during a second portion of the on-time period, and charge the gate of the power switch transistor through a third resistance during a third portion of the on-time period, wherein the second resistance is greater than the third resistance, wherein the gate drive control circuit comprises a first comparator configured to compare a gate voltage of the power switch transistor to a first threshold voltage;
- and a timer for timing a maximum duration period responsive to an initiation of the second portion of the on-time period.
Dependencies are inferred from the claim text.