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US 11,688,814 B2Granted
Semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorHiroyuki Shimbo
Life of this patent
Estimating the term…
Abstract
In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.
Claims20
A semiconductor integrated circuit device comprising
- a first standard cell constituting a NOR gate and including first and second p-type nanowire field effect transistors (FETs), and first and second n-type nanowire FETs,
- the first and second p-type nanowire FETs are connected together in series, and the first and second n-type nanowire FETs are connected together in parallel,
- each of the first and second p-type nanowire FETs and the first and second n-type nanowire FETs including:
- a nanowire extending along a first direction, the nanowire being a single nanowire or including a plurality of nanowires;
- first and second pads arranged at both ends of the nanowire in the first direction, and connected to the nanowire;
- and
- a gate electrode extending along a second direction perpendicular to the first direction, and surrounding a periphery of the nanowire, wherein:
- the first pad of the first p-type nanowire FET, the first pad of the second p-type nanowire FET, and the second pad of the second p-type nanowire FET are arranged at a first pitch in the first direction,
- the first pad of the first n-type nanowire FET, the first pad of the second n-type nanowire FET, and the second pad of the second n-type nanowire FET are arranged at the first pitch in the first direction,
- a cell width of the first standard cell that is a dimension of the first standard cell in the first direction is an integral multiplication of the first pitch, and
- the gate electrode of the first p-type nanowire FET and the gate electrode of the first n-type nanowire FET are integrally formed with each other as a first gate line extending in the second direction, the gate electrode of the second p-type nanowire FET and the gate electrode of the second n-type nanowire FET are integrally formed with each other as a second gate line extending in the second direction.
8 more elements
A semiconductor integrated circuit device comprising
- a first standard cell constituting a NOR gate and including first, second and third p-type nanowire field effect transistors (FETs), and first, second and third n-type nanowire FETs,
- the first, second and third p-type nanowire FETs are connected together in series, and the first, second and third n-type nanowire FETs are connected together in parallel, each of the first, second and third p-type nanowire FETs and the first, second and third n-type nanowire FETs including:
- a nanowire extending along a first direction, the nanowire being a single nanowire or including a plurality of nanowires;
- first and second pads arranged at both ends of the nanowire in the first direction, and connected to the nanowire;
- and
- a gate electrode extending along a second direction perpendicular to the first direction, and surrounding a periphery of the nanowire, wherein:
- the first pad of the first p-type nanowire FET, the first pad of the second p-type nanowire FET, the first pad of the third p-type nanowire FET, and the second pad of the third p-type nanowire FET are arranged at a first pitch in the first direction,
- the first pad of the first n-type nanowire FET, the first pad of the second n-type nanowire FET, the first pad of the third n-type nanowire FET, and the second pad of the third n-type nanowire FET are arranged at the first pitch in the first direction,
- a cell width of the first standard cell that is a dimension of the first standard cell in the first direction is an integral multiplication of the first pitch, and
- the gate electrode of the first p-type nanowire FET and the gate electrode of the first n-type nanowire FET are integrally formed with each other as a first gate line extending in the second direction, the gate electrode of the second p-type nanowire FET and the gate electrode of the second n-type nanowire FET are integrally formed with each other as a second gate line extending in the second direction, the gate electrode of the third p-type nanowire FET and the gate electrode of the third n-type nanowire FET are integrally formed with each other as a third gate line extending in the second direction.
7 more elements
Dependencies are inferred from the claim text.