Integrated circuit structure and method for forming the same

A method, comprising:

• forming a gate dielectric layer over a semiconductor substrate;
• forming a gate electrode over the gate dielectric layer;
• depositing a dielectric layer over the gate electrode and the gate dielectric layer, wherein the dielectric layer has a first portion extending along a top surface of the gate dielectric layer and a second portion extending along a sidewall of the gate electrode;
• forming a field plate electrode over the first portion of the dielectric layer, wherein the second portion of the dielectric layer is between the gate electrode and the field plate electrode;
• forming a spacer over the first portion of the dielectric layer and on a sidewall of the field plate electrode, wherein a top surface of the second portion of the dielectric layer is higher than a top end of the spacer;
• and
• after forming the spacer, forming source and drain features in the semiconductor substrate.

A method, comprising:

• forming a gate dielectric layer over a semiconductor substrate;
• forming a gate electrode over the gate dielectric layer;
• depositing a dielectric layer over the gate electrode and the gate dielectric layer;
• depositing a field plate electrode layer over the dielectric layer;
• etching the field plate electrode layer to form a first field plate electrode, wherein the first field plate electrode tapers away from the gate electrode;
• forming source and drain features in the semiconductor substrate;
• and
• forming a metal silicide layer over the first field plate electrode, wherein a first portion of the metal silicide layer adjacent to the gate electrode is higher than a second portion of the metal silicide layer away from the gate electrode.