Semiconductor device with controllable channel length and manufacturing method of semiconductor device with controllable channel length

A manufacturing method of a semiconductor device, the method comprising:

• forming a buried impurity layer in a substrate;
• forming a first deep well region, a second deep well region, and a third deep well region spaced apart from each other on the buried impurity layer;
• forming shallow isolation regions on the substrate;
• forming a first well region, a second well region, and a third well region on the first deep well region, the second deep well region, and the third deep well region, respectively;
• forming a first gate electrode disposed between the first well region and the second well region on the substrate;
• forming a second gate electrode disposed between the second well region and the third well region on the substrate;
• forming a first source region, a drain region, and a second source region on the first well region, the second well region, and the third well region, respectively;
• and
• forming deep trench isolation regions surrounding the first gate electrode and the second gate electrode,
• wherein the first gate electrode and the second gate electrode are connected to each other to form a ring-shaped gate electrode having an opening area in which the drain region is formed,
• wherein the first and second gate electrodes are disposed to overlap the shallow isolation regions and not overlap the second deep well region,
• wherein the shallow isolation regions are spaced apart from the P-type deep well region, and
• wherein each of the deep trench isolation regions has a depth greater than a depth of each of the first deep well region, the second deep well region, and the third deep well region.

A manufacturing method of a semiconductor device, the method comprising:

• forming an N-type buried impurity layer in a substrate;
• forming an N-type deep well region surrounding an outermost portion of the semiconductor device;
• forming a P-type deep well region spaced apart from the N-type deep well region, the P-type deep well region and the N-type deep well region being in direct contact with an upper surface of the N-type buried impurity layer;
• forming an N-type well region and a P-type well region in contact with the N-type deep well region and the P-type deep well region, respectively;
• forming a P-type drift region disposed between the N-type well region and the P-type well region, the P-type drift region abutting the N-type well region and the P-type well region and disposed on the P-type deep well region;
• forming a ring-shaped gate electrode having an opening area and overlapping the N-type well region and the P-type drift region;
• forming a first P-type source region and a second P-type source region on the N-type well region, and forming a P-type drain region on the P-type well region;
• and
• forming a deep trench isolation region surrounding the first source region and the second source region,
• wherein the ring-shaped gate electrode is disposed not to overlap with the P-type deep well region, and
• wherein the P-type drain region is formed in the opening area.